Transverse junction field effect transistor

ABSTRACT

A transverse JFET of SiC, employing an n + -type SiC substrate and comprising a channel region having carriers of high mobility, bringing a high yield is obtained. This transverse JFET has an n + -type SiC substrate, a p-type SiC film formed on a front face of the n + -type SiC substrate, an n-type SiC film, including a channel region, formed on the p-type SiC film, source and drain regions formed on the n-type SiC film separately on both sides of the channel region respectively, and a gate electrode provided on the SiC substrate or on the p-type SiC film.

CROSS REFERENCE TO RELATED APPLICATION

This application is a Continuation of U.S. application Ser. No.10/168,263 filed Jun. 19, 2002.

TECHNICAL FIELD

The present invention relates to a transverse junction field effecttransistor (JFET: Junction Field Effect Transistor), and morespecifically, it relates to a transverse junction field effecttransistor employed as a power transistor for electric power.

BACKGROUND TECHNIQUE

A junction field effect transistor (JFET) applies a reverse bias voltagefrom a gate electrode to a p-n junction provided on a side portion of achannel region passing carriers therethrough, thereby spreading adepletion layer from the p-n junction to the channel region andcontrolling the conductance of the channel region for performingoperation such as switching. In a “transverse” JFET, carriers move inparallel with an element face in the channel region. While the carriersfor the channel may be either electrons (n-type) or holes (p-type),mobility of electrons is higher as compared with holes in SiC to whichthe present invention is directed, and hence the channel region isgenerally formed by an n-type impurity region. For the purpose ofconvenience, therefore, it is assumed that the carriers for the channelare electrons and hence the channel region is an n-type impurity regionin the following description, while the channel region may alternativelybe formed by a p-type impurity region, as a matter of course.

SiC, having large mobility of carriers similarly to Si as describedabove, a high saturation drift velocity similarly to GaAs and a highwithstand voltage, is subjected to study for application to a high-speedswitching element or a high-power element. Crystal structures of SiCinclude a hexagonal closest packing structure and a cubic closestpacking structure, while the hexagonal closest packing structureincludes a number of structures having different cycle periods of layersand at least 100 polytypes are known. Representative polytypes are 3C,4H, 6H and the like. C means cubic and H means hexagonal, while theprefixed numerals express cycle periods. Only 3C is cubic and referredto as β-SiC, and the remailing polytypes are referred to as α-SiC as awhole. In the following description, only 6H or 4H of α-SiC is solelyemployed.

FIG. 34 is a sectional view showing an exemplary JFET employing SiC(U.S. Pat. No. 5,264,713 granted to John W. Palmour et al.). Referringto FIG. 34, the conductivity type of an SiC substrate 101 is preferablythe p-type, to define a p-type SiC substrate. The conductivity type ofan SiC film 102 formed on a partial region of the SiC substrate 101 isalso preferably the p-type, to define a p-type SiC film 102. Further, ann-type SiC film 103 is formed on this p-type SiC film 102 to include athinned portion 111 corresponding to a channel region. An n⁺-typeimpurity layer 117 coming into ohmic contact with a source electrode 112and an n⁺-type impurity layer 118 coming into ohmic contact with a drainelectrode 113 are formed on the n-type SiC film 103. A gate electrode114 is formed on the back side of the aforementioned p-type SiCsubstrate 101 as a back gate 114. Face portions excluding theaforementioned source, drain and gate electrodes are covered withprotective films 126.

In the aforementioned prior art (FIG. 34), the conductivity type of theSiC substrate is preferably set to the p-type for the following reason:As hereinabove described, carriers for the channel region are formed byelectrons (n-type), since high mobility is attained. Therefore, then-type SiC film defines a layer including the channel region. Thus, thep-type SiC film defines a layer limiting the carriers in this n-type SiCfilm in the periphery. If an n-type SiC substrate is employed as the SiCsubstrate for forming this p-type SiC film, a reverse bias voltage isapplied to the junction between the n-type SiC substrate and the p-typeSiC film to result in a depletion layer when a plus potential is appliedto the gate electrode. Therefore, it is necessary to evaluate anddetermine influence by this depletion layer. When the p-type SiCsubstrate is employed to the contrary, this influence by a depletionlayer may not be evaluated and no reverse bias voltage may be taken intoconsideration in the junction of the multilayer part reaching thechannel region in on-off action. When the SiC substrate of theaforementioned conductivity type is employed, therefore, a high-speedswitching element for high power or the like can be obtained withcarriers having high mobility by growing a depletion layer only in thechannel region at need.

However, the p-type SiC substrate has higher defect density ofmicropipes or the like as compared with the n-type SiC substrate.Therefore, the defect density is increased also in a crystal growthlayer essential in fabrication of the semiconductor element such as theJFET. Reflecting such high defect density, the JFET formed on the p-typeSiC substrate exhibits a low yield for defining a JFET of completequality, while a completed JFET exhibits a large leakage current.

In the aforementioned transverse JFET shown in FIG. 34, a forward biasvoltage is applied to the junction between the source region 103 formedby an n-type impurity region and the p-type impurity layer 102 in anON-state. In an OFF-state, a reverse bias voltage is applied to theaforementioned junction, and a depletion layer grows in the channelregion to block the channel region. In the ON-state, the forward biasvoltage is desirably applied to the junction between the source region103 formed by an n-type impurity region and the p-type impurity layer102, and a current escapes from the channel region and flows into thegate electrode 114. The current leaking from the channel region andflowing into the gate electrode 114 increases along with forward biasvoltage rise and temperature rise. The current leaking from the channelregion and flowing into the gate electrode exerts influence on theamplification factor, and the amplification factor is problematicallylowered when this current increases.

In the transverse JFET shown in FIG. 34, the aforementioned p-n junctionis formed on the overall face of the p-type epitaxial SiC film. Ascompared with the area of the part of the channel region in contact withthe bottom of a trench 124, therefore, the area of the aforementionedp-n junction between the n-type impurity region 103 and the p-typeimpurity region is problematically excessive. In other words, the ratioof a part not contributing to on-off action but defining the path forthe aforementioned current leaking from the channel region isproblematically large as compared with a small ratio of the area of thechannel region performing on-off action in the p-n junction.

FIG. 35 is a schematic sectional view of another conventional transverseJFET employing SiC (P. A Ivanov et al.: 4H-SiC Field-Effect TransistorHetero-Epitaxially Grown on 6H—SiC Substrate by Sublimation, p. 757,Silicon Carbide and Related Materials, 1995 Conf., Kyoto, Japan).Referring to FIG. 35, a 4H—SiC film 109 containing Sn ishetero-epitaxially grown on a 6H—SiC substrate 101, for defining abuffer layer 109. An SiC film 102 containing Al serving as a p⁺-typeimpurity is formed on the buffer layer 109, and an n-type SiC film 103containing nitrogen, having a channel region 111 arranged on the centralportion along with a source region 117 and a drain region 118 located onboth sides thereof is formed thereon. A source electrode 112 and a drainelectrode 113 are provided on upper portions of the left and right sidesof the channel region, and gate electrodes 114 are formed on portionsdownward beyond the source and drain electrodes through trenches 115. Nifilms defining underlayer films 120 and Al films defining upper films121 are formed as the electrodes 114. When this transverse JFET isemployed, a JFET having high drift mobility of electrons and extremelyhigh mobility of electrons can be formed.

However, the JFET shown in FIG. 35 has the following problems:

(a) The JFET is insufficient in points of high withstand voltage and lowON-state resistance.

The withstand voltage of a JEST depends on the withstand voltage of ap-n junction formed by an n-type impurity region defining a channel anda p-type impurity region in contact with this region. In order toimprove the withstand voltage of the JFET, therefore, the withstandvoltage of the p-n junction may be improved. While the concentration ofan n-type impurity defining the impurity in the channel may be reducedin order to improve the withstand voltage of the p-n junction, thequantity of a current in the channel is reduced and ON-state resistance(resistance in a state where carriers flow in the channel region) isincreased as a result. Consequently, power is consumed and the elementtemperature is increased. A transverse JFET exhibits a negativetemperature coefficient in a large drain current range and hencenegative feedback is applied with respect to temperature rise, while nonegative feedback is applied in a small drain current range. Powerconsumption in the element is unpreferable regardless of the value ofthe drain current. Another reason for the impossibility of reducing theaforementioned ON-state resistance of the JFET resides in contactresistance in the electrodes. When each electrode is made of Ni in thestructure shown in FIG. 35, impurity concentration is so low thatSchottky contact tends to remain and ohmic contact cannot be attained.

(b) The JFET is insufficient in switching speed.

The switching speed depends on the charge/discharge time for a depletionlayer in the p-n junction. Assuming that C represents the capacitance ofthe depletion layer and Rg represents gate resistance, thecharge/discharge time is substantially proportionate to the product CRgthereof. Therefore, the switching time can be quickened if the gateresistance Rg can be lowered, while the trenches are formed in thesecond conductivity region and the gate resistance cannot besufficiently lowered in the conventional JFET shown in FIG. 35. Whenattaching importance to intuitive grasp while slightly sacrificingcorrectness, the gate resistance Rg can be regarded as the resistance ofpaths reaching the p-n junction interface on the central portion of thechannel 111 from the gate electrodes 114.

(c) Fabrication steps are complicated and require precise and strictmanagement.

The aforementioned JFET shown in FIG. 35 is fabricated by the followingmethod: The buffer layer 109 is formed on the SiC substrate 101,followed by formation of the p⁺-type SiC film 102. Then, the n-type SiCfilm is formed for patterning portions formed with the channel, sourceand drain regions by RIE (reactive ion etching), as shown in FIG. 36.Then, the Ni films are formed as the underlayers 120 of the electrodes,as shown in FIG. 37. The Al films defining the upper layers 121 of theelectrodes are formed on the Ni films, as shown in FIG. 38. At thistime, the Al films may not be registrable immediately on the Ni filmsbut may be misregistered. When adhering to side walls or the like, Alacts as floating electrodes to unstabilize the element operation. Then,the portion between the source electrode 112 and the drain electrode 113is etched by RIE through the electrodes 112 and 113 serving as masks forforming the channel region 111, as shown in FIG. 39. At this time, theface of the p⁺ film 102 is also etched for defining the trenches 115along with the channel region. In this etching, Al or the like adheringdue to the aforementioned misregistration is also removed. Theelectrodes are formed by the two-layer films of the Ni films and the Alfilms, in order to form ohmic contact. The resistance Rg of the pathsreaching the p-n junction interface on the central portion of thechannel region from the gate electrodes is increased due to theaforementioned trenches, and the rise (fall) time is increased when theJFET is applied to a switching element. Further, additional man-hoursare required for forming the trenches, leading to increase of the cost.

(d) Transistor characteristics remarkably fluctuate in response todispersion of the impurity concentration, the thickness etc. of thechannel region. When a high-concentration impurity element is injectedfor reducing the electric resistance of the channel region in order toavoid such dispersion between elements, withstand voltage isdeteriorated. Therefore, awaited is a JFET, employing nohigh-concentration impurity, hardly influenced by dispersion of theimpurity concentration, the thickness etc. of the channel region.

(e) The aforementioned JFET is of a normally on type (enters an ON-statewhen no voltage is applied to the gate) in general, and the structure ofthe gate circuit is complicated when employed for controlling a rotarymachine or the like. In other words, the JFET enters an ON-state when novoltage is applied to the gate, and hence the rotary machine hazardouslyremains rotating if the gate circuit breaks down. In preparation forbreakdown, therefore, the gate circuit must be provided with a mechanismfor turning off the same upon breakdown. Further, a voltage must becontinuously applied in an OFF-state, and hence power consumption takesplace in the OFF-period.

(f) Operation is unstabilized due to surface charges with a largesurface leakage current.

A malfunction results from such surface charges or the surface leakagecurrent, to lower the yield.

The present invention has been proposed in order to solve theaforementioned problems, and a first object thereof is to obtain atransverse JFET of SiC bringing a high yield, employing an n-type SiCsubstrate and comprising a channel region having carriers exhibitinghigh mobility.

A second object of the present invention is to provide a transverseJFET, which is easy to fabricate, has low loss and is excellent inwithstand voltage and high-speed switching characteristics.

A third object of the present invention is to provide a transverse JFETsuppressing a current leaking from a channel region in an ON-state tocause no reduction of the amplification factor.

Disclosure of the Invention

A transverse JFET according to a first aspect of the present inventioncomprises an n-type SiC substrate, a p-type SiC film formed on the rightface of the n-type SiC substrate, an n-type SiC film, including achannel region, formed on the p-type SiC film, source and drain regionsformed on the n-type SiC film separately on both sides of the channelregion respectively, and a gate electrode provided in contact with then-type SiC substrate.

According to the aforementioned structure, a JFET driving carriersexhibiting high mobility can be prepared with a high yield whileemploying an n-type SiC substrate having low defect density. In thiscase, presence/absence of a problem depends on whether the JFET is in anON-state or in an OFF-state. The significance of the transverse JFETaccording to the first aspect of the present invention resides in thatthe transverse JFET is prepared on the n-type SiC substrate, and henceit is premised that the n-type and the p-type are not replaced with eachother only in the transverse JFET according to the first aspect of thepresent invention. To the contrary, the remaining aspects of the presentinvention hold also when the n-type and the p-type are replaced witheach other, and hence replacement of the n-type and the p-type isassumed.

In an OFF-state of a normally on JFET, a negative gate voltage isapplied and hence no problem arises. In other words, a forward biasvoltage is applied to the junction between the n-type SiC substrate andthe p-type SiC film in the OFF-state, and hence no depletion layer isformed on this junction. In the aforementioned OFF-state, a reverse biasvoltage is applied to only the junction between the p-type SiC film andthe n-type SiC film, and a depletion layer spreads in the channel regionhaving a low impurity concentration to block a carrier path.

In an OFF-state of a normally off JFET, built-in potentials aregenerated in the junction between the n-type SiC substrate and thep-type SiC film and the junction between the p-type SiC film and then-type SiC film respectively to form depletion layers, while the sameindividually spread respectively to cause no problem.

In an ON-state of the normally on JFET, the gate voltage may be set to 0V, while a depletion layer spreads due to a built-in potential. In orderto feed a larger quantity of current, a plus potential must be suppliedto the gate in order to eliminate the depletion layer resulting from thebuilt-in potential. Therefore, study is required as to the depletionlayer formed following application of the plus potential to the gate.When the potential of the gate electrode is plus, a reverse bias voltageis applied to the junction between the n-type SiC substrate and thep-type SiC film. When both of the impurity concentration of the n-typeSiC substrate and the impurity concentration of the p-type SiC film areincreased, however, the width of the depletion layer is reduced.Therefore, a current flows through the depletion layer due to tunneling.Withstand voltage of the junction may disappear due to the increasedimpurity concentrations, to result in flow of a current. Therefore, thedepletion layer in the aforementioned junction hardly influences theoperation. In order to obtain the aforementioned junction, the n-typeimpurity concentration of the n-type SiC substrate may be set to about1×10¹⁹ cm⁻³, and the p-type impurity concentration of the p-type SiCfilm may be set to about 1×10¹⁹ cm⁻³. Consequently, a JFET of SiCcapable of high-speed operation such as high-speed switching can beprepared by improving the yield from preparation of the SiC substrate tocompletion of the product.

In an ON-state of the normally off JFET, a phenomenon similar to that inthe ON-state of the aforementioned normally on JFET takes place, andhence no particular problem arises as described above.

A voltage is applied in the following manner in response to whether theJFET is normally on or normally off, for performing on-off action: Inthe normally on JFET, the gate voltage is varied in the range of minus(off) to plus (on). In the normally off JFET, the gate voltage is variedin the range of zero (off) to plus (on). The normally off JFET isimplemented by satisfying prescribed requirements as to the impurityconcentrations and the structures, as described above.

In the JFET according to the aforementioned first aspect of the presentinvention, a region of the p-type SiC film can include a region of then-type SiC film as viewed in plane, for example.

According to this structure, an end face of the n-type SiC film islocated inside the end face of the p-type SiC film forming theunderlayer as viewed in plane. In other words, a step is providedbetween the p-type SiC film and the n-type SiC film located thereon. Theend faces of these SiC films are generally formed by RIE (reactive ionetching). In the structure that the end face of the n-type SiC film andthe end face of the p-type SiC film align with each other as in theprior art, the end face of the n-type SiC film is continuously exposedto ions when both the n-type SiC film and the p-type SiC film formingthe underlayer therefor are etched. In the aforementioned structure, onthe other hand, the end face of the n-type SiC film is formed by secondetching after etching the end face of the p-type SiC film. Therefore,this end face is exposed to ions only in a short period for the secondetching. Consequently, the end face of the n-type SiC film including thechannel, source and drain regions is exposed to ions for a short time tohardly result in deterioration of a surface crystal layer remarkablyinfluencing transistor characteristics.

In the JFET according to the aforementioned first aspect of the presentinvention, the gate electrode is arranged on the right face of then-type SiC substrate in the vicinity of an end of the p-type SiC film,for example.

According to this structure, the JFET can be prepared by a simplepreparation method, while an OFF-state can be implemented by reliablyapplying a reverse bias voltage to the junction between the p-typesemiconductor film and the channel region (the n-type semiconductorfilm) and forming a depletion layer.

In the JFET according to the aforementioned first aspect of the presentinvention, the gate electrode is formed on the back side of the n-typeSiC substrate, for example, and arranged in a back gate structure.

A signal for applying a gate voltage is linearly transmitted to thechannel region from the front face of the channel region in a wide rangedue to employment of the aforementioned back gate structure, whereby theswitching speed can be improved. Further, the gate electrode is notarranged on a position spreading from the channel region butstereoscopically arranged in superposition with the channel region,whereby the degree of integration of the JFET can be improved. Also inthe back gate structure, a depletion layer is formed on the junctionbetween the n-type SiC substrate and the p-type SiC film due toapplication of a plus voltage to the gate. However, this depletion layercan be prevented from influencing the operation of the JFET by improvingthe impurity concentrations on both sides, as described above.

In the JFET according to the first aspect of the present invention, thethickness of the channel region is rendered smaller than the width of adepletion layer in the n-type SiC film resulting from a built-inpotential on the junction between the p-type SiC film and the n-type SiCfilm formed on the p-type SiC film, for example.

According to this structure, a depletion layer is formed on the junctionbetween the p-type SiC film and the n-type SiC film when the gatepotential is zero, and the forward end of the width of the depletionlayer exceeds the thickness of the channel region. Therefore, thechannel region is deenergized and an OFF-state is implemented when thegate voltage is zero.

The JFET according to the aforementioned first aspect of the presentinvention can further comprise a low-concentration n-type SiC film, heldin contact between the p-type SiC film and the n-type SiC film,containing an n-type impurity of a lower concentration than the n-typeimpurity concentration of the channel region, for example.

According to this structure, a transverse JFET having high withstandvoltage can be obtained with an n-type SiC substrate having low defectdensity, without influencing a current in the channel region. Thus, atransverse JFET exhibiting small power consumption and low temperaturerise also when fed with a high current can be fabricated at a low cost.

In the JFET according to the aforementioned first aspect of the presentinvention, the channel region can contain an n-type impurity of a higherconcentration than the impurity concentration of portions of the n-typeSiC film located on both sides thereof, for example.

According to this structure, a depletion layer can be formed to closesections of the channel on both sides of the channel region with then-type SiC substrate having low defect density for attaining anOFF-state so that the portion of the depletion layer withstands thevoltage. Therefore, ON-state resistance can be reduced without reducingthe withstand voltage of the transverse JFET, which can be employed as aswitching element having high withstand voltage with low loss.

The JFET according to the aforementioned first aspect of the presentinvention can have a conductor film arranged in contact with the face ofthe channel region, for example.

According to this structure, the channel region and the conductor filmare arranged in parallel with respect to a current flowing through thechannel. Therefore, when the electric resistance of the conductor filmis lower by 1 order as compared with the channel region, for example, acurrent flowing through the conductor film in an ON-state is increasedby about 10 times as compared with that flowing through the channelregion. Also when the impurity concentration or the thickness of thechannel region is dispersed, therefore, influence exerted on thetransistor characteristics is so small that influence by dispersion ofsuch a factor substantially causes no problem. In an OFF-state, on theother hand, a depletion layer extends toward the n-type SiC film in thejunction between the n-type SiC film including the channel region andthe p-type SiC film defining the underlayer therefor due to a negativepotential (reverse bias voltage) applied to the gate electrode. Thisdepletion layer more widely expands toward a side having lowerconcentration in proportion to the aforementioned reverse bias voltageand in inverse proportion to the impurity concentrations of the n-typeSiC film including the channel region and the p-type SiC film serving asthe underlayer therefor. When this depletion layer blocks the channelregion, the path for carriers passing through the channel region isblocked. Consequently, the OFF-state can be readily implemented.

When the JFET according to the aforementioned first aspect of thepresent invention comprises the conductor film, the length of theconductor film along the channel length direction can be renderedsmaller than a channel length, for example.

At least an end of the conductor film is insulated from a side wall, andhence the JFET can be turned off by deenergizing the channel region onthe side insulated from the depletion layer.

When the JFET according to the aforementioned first aspect of thepresent invention comprises the conductor film, the thickness of thechannel region can be rendered smaller than the width of a depletionlayer in the n-type SiC film resulting from a built-in potential on thejunction between the p-type SiC film and the n-type SiC film formed onthe p-type SiC film, for example.

When the gate potential is zero, the depletion layer formed on thejunction between the p-type SiC film and the n-type SiC film due to thebuilt-in potential blocks the channel region. Therefore, a normally offtransverse JFET can be obtained and can be employed for controlling arotary machine or the like without taking countermeasures againstbreakdown of the gate circuit or the like. Further, power consumptioncan be reduced in the ON-state, and influence by dispersion of theimpurity concentration of the channel region or the like can be avoided.

When the JFET according to the aforementioned first aspect of thepresent invention comprises the conductor film, the conductor film canbe either a metal film or a semiconductor film containing ahigh-concentration impurity, for example.

According to the aforementioned structure, a parallel bypass of lowresistance can be simply provided on the channel region with a metalfilm of low resistance. The metal film may be made of any material sofar as the same serves as an electrode material, while aluminum (Al) oran aluminum alloy is desirable in consideration of easiness of etchingand high conductivity.

In the JFET according to the aforementioned first aspect of the presentinvention, the SiC substrate is a 6H—SiC substrate, and both of thep-type SiC film and the n-type SiC film are made of 6H—SiC.

According to this structure, thin films having excellent crystallinityare stacked so that the yield is not reduced due to a malfunction or thelike resulting from poor crystallinity.

In the JFET according to the aforementioned first aspect of the presentinvention, both of the p-type SiC film and the n-type SiC film can bemade of 4H—SiC, and the p-type SiC film consisting of 4H—SiC can beformed on a 6H—SiC substrate through a buffer layer of 4H—SiC, forexample.

A 4H—SiC film having excellent crystallinity can be obtained by thebuffer layer while 4H—SiC exhibits mobility of electrons superior tothat in 6H—SiC or the like, whereby the JFET can be rendered suitable toa high-speed switching element or the like.

In the JFET according to the aforementioned first aspect of the presentinvention, the SiC substrate can be a 4H—SiC substrate, and both of thep-type SiC film and the n-type SiC film can be made of 4H—SiC, forexample.

According to the aforementioned structure, thin films having excellentcrystallinity are stacked, and the yield or the like is not reduced dueto a malfunction or the like resulting from poor crystallinity. Further,4H—SiC exhibits mobility of electrons superior to that in 6H—SiC or thelike as described above, whereby the JFET can be rendered suitable to ahigh-speed switching element or the like.

In the JFET according to the aforementioned first aspect of the presentinvention, both of the p-type SiC film and the n-type SiC film can bemade of 6H—SiC, and the p-type SiC film consisting of 6H—SiC can beformed on a 4H—SiC substrate through a buffer layer of 6H—SiC, forexample.

A 6H—SiC film having excellent crystallinity can be obtained by thebuffer layer, and SiC of a proper crystal type can be employed inresponse to application.

The significance of the transverse JFET according to the first aspect ofthe present invention resides in that the transverse JFET is prepared onthe n-type SiC substrate as hereinabove described, and hence it ispremised that the n-type and the p-type are not replaced with each otheronly in the transverse JFET according to the first aspect of the presentinvention. To the contrary, transverse JFETs according to thosefollowing a second aspect of the present invention hold also when then-type and the p-type are replaced with each other, and hence theconductivity type of an impurity is referred to as a first conductivitytype or a second conductivity type. The first conductivity type may beeither the p-type or the n-type, and the second conductivity type may beeither the n-type or the p-type.

The transverse JFET according to the second aspect of the presentinvention comprises an SiC substrate, a second conductivity type SiCfilm formed on the SiC substrate, a first conductivity type SiC filmformed on the second conductivity type SiC film, a channel region formedby reducing the thickness of the first conductivity type SiC film, asource region and a drain region, films consisting of first conductivitytype SiC formed on the first conductivity type SiC film, separatelyformed on both sides of the channel region respectively, and a gateelectrode, and the gate electrode is formed on a flat region of secondconductivity type SiC.

According to this structure, the gate is formed on the flat region ofthe second conductivity type SiC, whereby gate resistance can be reducedand a speed of response in switching can be increased as a result.Further, slight misregistration in formation of the gate electrodecauses no problem in a fabrication step, whereby the yield can beprevented from reduction. Thus, the JFET can be applied to a high-speedswitching element.

In the transverse JFET according to the aforementioned second aspect ofthe present invention, the second conductivity type SiC film has anuntrenched face, and the gate electrode consists of two gate electrodesformed on the flat face of the second conductivity type SiC film formingthe flat region of second conductivity type SiC, for example.

According to this structure, no trenches or the like are providedbetween the source and drain regions and the gate, whereby gateresistance can be reduced and the speed of response in switching can beimproved as a result. Further, slight misregistration in formation ofthe gate electrode causes no problem in a fabrication step, whereby theyield can be prevented from reduction.

In the transverse JFET according to the aforementioned second aspect ofthe present invention, the SiC substrate is a second conductivity typeSiC substrate containing a second conductivity type impurity, and thegate electrode is formed in a back gate structure provided on the backside of the second conductivity type SiC substrate forming the flatregion of second conductivity type SiC, for example.

According to this structure, the gate electrode is provided on theoverall back side of the second conductivity type SiC substrate, wherebygate resistance is reduced. Consequently, the speed of response inswitching is improved, and the JFET can be employed as a high-speedswitching element. Further, the gate electrode can be readily formed.

The transverse JFET according to the aforementioned second aspect of thepresent invention preferably further comprises a low-concentration firstconductivity type SiC film, held in contact between the secondconductivity type SiC film and the first conductivity type SiC film,containing a first conductivity type impurity of a lower concentrationthan the first conductivity type impurity concentration of the channelregion.

According to this structure, withstand voltage can be improved withoutexerting influence on a current in the channel region. Therefore, highwithstand voltage can be attained with small power consumption withoutincreasing the temperature also when feeding a high current.Consequently, the JFET can be applied to a high-voltage and high-powerswitching element.

In the transverse JFET according to the aforementioned second aspect ofthe present invention, the channel region can contain a firstconductivity type impurity of a higher concentration than the impurityconcentration of portions of the first conductivity type SiC filmlocated on both sides thereof.

According to this structure, a depletion layer is formed to dosesections of the channel from both sides of the channel region forattaining an OFF-state so that the portion of the depletion layerwithstands the voltage, whereby ON-state resistance can be reducedwithout reducing the withstand voltage of the transverse JFET.Therefore, this transverse JFET, consuming no power also when fed with ahigh current, can be employed as a switching element having highwithstand voltage with low loss.

In the transverse JFET according to the aforementioned second aspect ofthe present invention including the low-concentration first conductivitytype SiC film, the channel region contains a first conductivity typeimpurity of a higher concentration than the impurity concentration ofportions of the first conductivity type SiC film located on both sidesthereof.

According to this structure, ON-state resistance can be reduced withoutremarkably reducing the withstand voltage of the transverse JFET.Consequently, the JFET can be applied to a high-voltage high-powerswitching element.

In the transverse JFET according to the aforementioned second aspect ofthe present invention, the thickness of the channel region is smallerthan the width of a depletion layer in the first conductivity type SiCfilm resulting from a built-in potential on the junction between thesecond conductivity type SiC film and the first conductivity type SiCfilm formed on the second conductivity type SiC film, for example.

According to the aforementioned structure, a normally off JFET can beobtained by spreading the depletion layer resulting from a built-inpotential on the junction between the channel region (first conductivitytype semiconductor layer) and the second conductivity type semiconductorlayer located under the same, for example. In this transverse JFET, theimpurity concentration of the channel region is not more than 5×10¹⁶cm⁻³, and the thickness of the channel region is set to not more than550 nm, for example. When setting the impurity concentration of thechannel region to not more than 5×10¹⁶ cm⁻³ while setting the impurityconcentration in the second conductivity type SiC film to ageneral-level concentration higher than the same, the width of theaforementioned depletion layer exceeds 550 nm. Therefore, a state wherethe depletion layer extending in the channel region blocks this channelregion is implemented with a gate voltage of zero. In other words, anormally off JFET can be obtained and the aforementioned JFET can beloaded on a rotary machine or the like without providing a circuitemploying a complicated countermeasure against breakdown of the gatecircuit.

In order to attain an ON-state, a positive potential overcoming thebuilt-in potential may be applied. A built-in potential generated in athermal equilibrium state is 2 V to 3 V in general, and hence theaforementioned depletion layer is removed and the channel region isrendered conductive when a positive potential of 2 V to 3 V is suppliedto the gate electrode. The applied potential in the aforementionedOFF-state is 0 V, and hence off-time power consumption can be remarkablyreduced as compared with an applied potential of about 22 V necessaryfor turning off a normally on JFET. Consequently, a JFET having lowpower consumption readily loadable on a rotary machine or the like canbe provided while ensuring a high-speed switching function with low lossand high withstand voltage.

In the transverse JFET having the channel region containing the firstconductivity type impurity in a higher concentration than the impurityconcentration of the portions of the first conductivity type SiC filmlocated on both sides thereof according to the aforementioned secondaspect of the present invention, the thickness of the channel region isrendered smaller than the width of a depletion layer in the firstconductivity type SiC m resulting from a built-in potential on thejunction between the second conductivity type SiC film and the firstconductivity type SiC film formed on the second conductivity type SiCfilm, for example.

This structure implements a state where the depletion layer extendingtoward the first conductivity type SiC film on the side portion of thechannel region blocks the channel region with a gate voltage of zero.The depletion layer may block one side of the channel region, or mayblock both sides of the channel region. Therefore, a normally off JFETis obtained and can be employed without forming a complicated mechanismfor a countermeasure against breakdown of the gate circuit forcontrolling a rotary machine or the like.

The transverse JFET according to the aforementioned second aspect of thepresent invention can have a conductor film arranged in contact with theface of the channel region.

According to the aforementioned structure, the channel region and theconductor film are arranged in parallel with respect to a currentflowing through the channel. Therefore, when the electric resistance ofthe conductor film is lower by 1 order as compared with the channelregion, for example, a current flowing through the conductor film in anON-state is higher by about 10 times as compared with that in thechannel region. Also when the impurity concentration or the thickness ofthe channel region is dispersed, therefore, only slight influence isexerted on the transistor characteristics such that influence bydispersion of such factors substantially causes no problem. In theOFF-state, on the other hand, the depletion layer extends toward thefirst conductivity type semiconductor layer on the junction between thefirst conductivity type semiconductor layer including the channel regionand the second conductivity type semiconductor layer located under thesame due to the negative potential (reverse bias voltage) applied to thegate electrode. This depletion layer more widely expands toward a sidehaving a lower concentration in proportion to the aforementioned reversebias voltage and in inverse proportion to the impurity concentration ofthe first conductive layer and the second conductive layer. When thisdepletion layer blocks the channel region, a path for carriers passingthrough the channel region is blocked. When the aforementioned conductorfilm is so arranged that the side portions thereof are not in contactwith the portions of the first conductivity type semiconductor layerholding the channel region therebetween, for example, not only thechannel region but also the conductor film is deenergized by theaforementioned deenergization. Consequently, the OFF-state can bereadily implemented. Also when the aforementioned conductor film is incontact with only one side of the aforementioned first conductivity typesemiconductor layer without coming into contact with the other side, theaforementioned OFF-state can be readily implemented and the resistancecan be reduced. This reduction of the resistance reduces influence bydispersion of the impurity concentration or dispersion of the thicknessof the channel region. When both sides of the aforementioned conductorfilm are in contact with the aforementioned first conductivity typesemiconductor layer respectively, the resistance is further reduced, tobe more hardly influenced by dispersion of the aforementioned impurityconcentration or dispersion of the thickness of the channel region. Thefirst conductivity type may be either the n-type or the p-type, and thesecond conductivity type may be either the p-type or the n-type.Further, the semiconductor substrate may be either an n-type Sisubstrate or a p-type Si substrate, or may be either an n-type SiCsubstrate or a p-type SiC substrate.

In the transverse JFET according to the aforementioned second aspect ofthe present invention, the length of the conductor film along thechannel length direction is preferably rendered smaller than a channellength.

According to this structure, difficulty in attainment of OFF action canbe eliminated when both ends of the conductor film are in contact withside walls. In other words, at least an end of the aforementionedconductor film is insulated from the side wall, and hence the JFET canbe turned off by blocking the channel region on the side where thedepletion layer is insulated.

In the transverse JFET according to the aforementioned second aspect ofthe present invention, the thickness of the channel region is renderedsmaller than the width of a depletion layer in the first conductivitytype SiC film resulting from a built-in potential on the junctionbetween the second conductivity type SiC film and the first conductivitytype SiC film formed on the second conductivity type SiC film.

According to the aforementioned structure, the depletion layer generatedon the junction between the second conductivity type semiconductor filmand the first conductivity type semiconductor film due to the built-inpotential blocks the channel region when the gate potential is zero.Therefore, a normally off JFET can be obtained and can be employed forcontrolling a rotary machine or the like without a countermeasureagainst breakdown of the gate circuit. Further, power consumption can bereduced in the ON-state, and influence by dispersion of the impurityconcentration of the channel region or the like can be avoided.

In the transverse JFET according to the aforementioned second aspect ofthe present invention, the conductor film is either a metal film or asemiconductor film containing a high-concentration impurity, forexample.

According to the aforementioned structure, a parallel bypass of lowresistance can be readily provided on the channel region with a metalfilm of low resistance. The metal film may be made of any material sofar as the same serves as an electrode material, while aluminum (Al) oran aluminum alloy is desirable in consideration of easiness of etchingand high conductivity.

In the transverse JFET according to the aforementioned second aspect ofthe present invention, the source region and the drain region cancontain a first conductivity type impurity of a higher concentrationthan the impurity concentration of portions of the first conductivitytype SiC film located on both sides of the channel region.

According to this structure, the ON-state resistance can be reducedwithout reducing the withstand voltage. Further, ohmic contact can beformed without bringing the electrode into a two-layer structureemploying Ni and Al or the like. Therefore, no trenches may be formed ina fabrication step as a result. Consequently, gate resistance can besuppressed and a rise (fall) time in switching can be reduced.

In the transverse JFET according to the aforementioned second aspect ofthe present invention, the impurity concentration of the secondconductivity type SiC film can exceed 10¹⁹ cm⁻³.

According to this structure, ohmic contact in the gate electrode holdsand the gate resistance is reduced also in a case of a single-layerelectrode of Ni or the like. Therefore, a rise time or a fall time inswitching can be reduced, and high-speed response is enabled.

In the transverse JFET according to the aforementioned second aspect ofthe present invention, a source electrode formed on the source region, adrain electrode formed on the drain region and the gate electrode formedon the second conductivity type SiC film or the second conductivity typeSiC substrate are preferably made of metals coming into ohmic contactwith SiC, containing impurities, in contact with the respectiveelectrodes.

According to this structure, the electrodes can be formed through simplesteps. In other words, electrode plates may have a single-layerstructure, and may not have a two-layer structure or the like.Therefore, no trenches for increasing gate resistance are formed as aresult, and the rise (fall) time in switching can be reduced. Metalsforming ohmic contact with the second conductivity type and firstconductivity type SiC films containing impurities in high concentrationsinclude Ni and the like.

In the transverse JFET according to the aforementioned second aspect ofthe present invention, a face portion excluding the source electrode, adrain electrode and the gate electrode is preferably covered with aninsulating film.

When the element face is exposed, unstable operation results from asurface leakage current or formation of surface charges. Switchingoperation can be stably carried out while preventing such trouble due tothe covering with the aforementioned insulating film.

In the transverse JFET according to the aforementioned second aspect ofthe present invention, the SiC substrate:is a 6H—SiC substrate, and bothof the second conductivity type SiC film and the first conductivity typeSiC film are made of 6H—SiC, for example.

According to the aforementioned structure, thin films having excellentcrystallinity are stacked and no reduction of the yield or the like iscaused due to a malfunction or the like resulting from poorcrystallinity.

In the transverse JFET according to the aforementioned second aspect ofthe present invention, both of the second conductivity type SiC film andthe first conductivity type SiC film are made of 4H—SiC, and the secondconductivity type SiC film consisting of 4H—SiC is formed on a 6H—SiCsubstrate through a buffer layer of 4H—SiC, for example.

A 4H—SiC film having excellent crystallinity can be obtained by thebuffer layer, and the mobility of electrons in 4H—SiC is superior tothat in 6H—SiC or the like, whereby the JFET can be rendered suitable toa high-speed switching element or the like.

In the transverse JFET according to the aforementioned second aspect ofthe present invention, the SiC substrate is a 4H—SiC substrate, and bothof the second conductivity type SiC film and the first conductivity typeSiC film are made of 4H—SiC, for example.

According to the aforementioned structure, thin films having excellentcrystallinity are stacked and no reduction of the yield or the like iscaused due to a malfunction or the like resulting from poorcrystallinity. Further, the mobility of electrons in 4H—SiC is superiorto that in 6H—SiC or the like as hereinabove described, whereby the JFETcan be rendered suitable to a high-speed switching element or the like.

In the transverse JFET according to the aforementioned second aspect ofthe present invention, both of the second conductivity type SiC film andthe first conductivity type SiC film are made of 6H—SiC, and the secondconductivity type SiC film consisting of 6H—SiC is formed on a 4H—SiCsubstrate through a buffer layer of 6H—SiC, for example.

A 6H—SiC film having excellent crystallinity can be obtained by thebuffer layer, and SiC of a proper crystal type can be employed inresponse to application.

A transverse JFET according to a third aspect of the present inventioncomprises an SiC substrate, having a gate electrode, of a conductivitytype of either a first conductivity type or a second conductivity typereverse thereto, a first SiC film formed on the SiC substrate, and afirst conductivity type second SiC film, formed on the first SiC film,including a channel region reduced in thickness and source and drainregions holding the channel region from both sides. In this transverseJFET, the first SiC film consists of a high-concentration impurityregion, provided on a portion located under the channel region, having awidth substantially identical to the width of the channel region and alength smaller than the length of the channel region and containing asecond conductivity type impurity in a higher concentration than thevalue of the first conductivity impurity concentration of the channelregion and a high-resistance region, other than the high-concentrationimpurity region, having high electric resistance.

The aforementioned high-concentration impurity region forms a junctionbetween the same and the channel region and forms a high potentialbarrier against carriers, while the carriers penetrate into thehigh-concentration impurity region due to tunneling or the like. Thecarriers penetrating into the high-concentration impurity regionrecombine with the high-concentration impurity to annihilate and form awattless leakage current, disadvantageously reducing the amplificationfactor. Such a wattless leakage current tends to increase as the forwardbias voltage is increased and the temperature is increased. Therefore,the length of the high-concentration impurity region is reduced beyondthat of the channel region for reducing the sectional area along thethickness direction, thereby increasing electric resistance of thehigh-concentration impurity region along the thickness direction. Theremaining portion of the first SiC film other than thehigh-concentration impurity region is rendered to define ahigh-resistance region despite a large sectional area along thethickness direction. This high-resistance region is so provided that thequantity of currents leaking from the source and carrier regions to thefirst SiC film can be reduced as compared with a case of rendering theoverall portion to define the aforementioned high-concentration impurityregion without providing this. In other words, the electric resistanceof the first SiC film in contact with the source region and the channelregion is increased as a whole, thereby suppressing currents leakingfrom the source region and the channel region to the first SiC film inthe ON-state. Therefore, most current flows from the source region intothe drain region through the channel region. On the other hand, theOFF-state is implemented by a depletion layer extending to the channelregion and deenergizing the channel region by applying a reverse biasvoltage to the junction between the aforementioned high-concentrationimpurity region and the channel region. The longitudinal direction ofthe channel region is regarded as the length, the directionperpendicular to the stacked faces is regarded as the thicknessdirection, and the direction perpendicular to these directions isregarded as the direction of width of the transverse JFET.

The aforementioned gate electrode may be provided either on the backside of the SiC substrate or on portions of the SiC substrate located onboth sides of the aforementioned first SiC film. The SiC substratepreferably contains the impurity in high concentration regardless of thefirst or second conductivity type, in order to enable ohmic contact withthe gate electrode.

Growth of the depletion layer to the channel region upon application ofthe reverse bias voltage is simplified as the ratio between the secondconductivity type impurity concentration of the high-concentrationimpurity region and the first conductivity type impurity concentrationof the channel region is increased. Therefore, the high-concentrationimpurity region containing the impurity of the reverse conductivity typeto the channel region in higher concentration than the value of theimpurity concentration in the channel region is provided, while thelength thereof is reduced below that of the channel region since thesectional area with respect to the thickness direction must be reducedfor increasing the electric resistance. The sectional area with respectto the thickness direction is reduced as the length of thehigh-concentration impurity region is reduced, such that the currentflowing into the gate electrode can be suppressed to a degree causing noproblem in practice by setting the length to not more than about 1 μm,for example. If the length is excessively reduced, however, thedepletion layer hardly blocks the channel region and carriers passthrough the depletion layer due to tunneling even if the depletion layerblocks the channel region, and hence the length is set to at least alevel capable of implementing the OFF-state due to formation of thedepletion layer.

Consequently, the currents leaking from the source and channel regionsto the first SiC film can be suppressed for preventing the amplificationfactor from reduction.

In the transverse JFET according to the aforementioned third aspect ofthe present invention, the high-resistance region contains a firstconductivity type impurity having a concentration value lower than thevalue of the first conductivity type impurity concentration of thesecond SiC film, for example.

Any of the following four structures corresponds to the aforementionedstructure: (a) A case where the channel region and the high-resistanceregion are of the n-type and the substrate (gate) is of the p-type, (b)a case where the channel region and the high-resistance region are ofthe n-type and the substrate (gate) is of the n-type, (c) a case wherethe channel region and the high-resistance region are of the p-type andthe substrate (gate) is of the n-type, and (d) a case where the channelregion and the high-resistance region are of the p-type and thesubstrate (gate) is of the p-type. In the cases (b) and (d) among these,i.e., when the high-resistance region and the substrate are of the sameconductivity type, no depletion layer is formed on the junction betweenthe high-resistance region and the substrate but the aforementionedleakage current is suppressed by high resistance resulting from lowimpurity concentration.

In the cases (a) and (c), i.e., when the high-resistance region and thesubstrate are of different conductivity types, on the other hand, thefollowing takes place: In the case (a), a plus potential is applied tothe gate in the ON-state. In the case (c), a minus potential is appliedto the gate in the ON-state. In both cases (a) and (c), therefore, thesubstrate and the high-resistance layer in the first SiC film areforward-biased to spread no depletion layer. Also in the cases (a) and(c), the aforementioned leakage current can be suppressed due to thehigh-resistance layer resulting from the low impurity concentration.

In any of the aforementioned cases, most current flows from the sourceregion to the drain region via the channel region in the ON-state.Therefore, reduction of the amplification factor can be prevented bysuppressing wattless currents leaking from the source and channelregions to the first SiC film. In the aforementioned transverse JFET,the low concentration value in the impurity concentration in thehigh-resistance region is preferably set to not more than 1×10¹⁷ cm⁻³.When the low concentration value of the first conductivity type orsecond conductivity type impurity in the aforementioned high-resistanceregion is set to not more than 1×10¹⁷ cm⁻³, the electric resistance canbe remarkably increased due to formation of the depletion layer, or theelectric resistance can be increased without forming the depletionlayer.

In the transverse JFET according to the aforementioned third aspect ofthe present invention, the high-resistance region contains a secondconductivity type impurity having a concentration value lower than thevalue of the first conductivity type impurity concentration of thesecond SiC film, for example.

Any of the following four cases corresponds to the aforementionedstructure: (e) A case where the channel is of the n-type, thehigh-resistance region is of the p-type and the substrate (gate) is ofthe p-type, (f) a case where the channel is of the n-type, thehigh-resistance region is of the p-type and the substrate (gate) is ofthe n-type, (g) a case where the channel is of the p-type, thehigh-resistance region is of the n-type and the substrate (gate) is ofthe n-type, and (h) a case where the channel is of the p-type, thehigh-resistance region is of the n-type and the substrate (gate) is ofthe p-type. In the cases (e) and (g) among these, i.e., when thehigh-resistance region and the substrate are of the same conductivitytype, no depletion layer is formed on the junction between thehigh-resistance region and the substrate but the aforementioned leakagecurrent can be suppressed due to high resistance resulting from thelow-concentration impurity.

In the cases (f) and (h) (when the high-resistance region and thesubstrate are of different conductivity types), on the other hand, adepletion layer is formed on the junction between the substrate and thehigh-resistance region in the ON-state. In other words, the substrate isof the p-type and forms an n-p⁻ junction with the high-resistance regionin the case (f), while the substrate is of the p-type and forms a p-n⁻junction with the high-resistance region in the case (h). In the case(f) (when the first conductivity type is set to the n-type), a zero orslightly plus potential is applied to the gate electrode in theON-state. In the case (h) (when the first conductivity type is set tothe p-type), a zero or slightly minus potential is applied to the gateelectrode in the ON-state. At this time, it follows that a reverse biasvoltage is applied to each of the aforementioned n-p⁻ and p-n⁻junctions, to result in a depletion layer. The electric resistance ofthe path from the channel region toward the first SiC film is extremelyincreased due to this depletion layer in addition to the high resistanceresulting from the low-concentration impurity.

Consequently, the wattless currents leaking from the source and channelregions to the first SiC film are suppressed and the amplificationfactor is prevented from reduction.

In the transverse JFET according to the aforementioned third aspect ofthe present invention, the high-resistance region consists of atwo-layer structure of a first layer and a second layer, for example,the first layer contains a first conductivity type impurity having aconcentration value lower than the value of the first conductivity typeimpurity concentration of the second SiC film, and the second layercontains the first conductivity type impurity having a concentrationvalue lower than the value of the first conductivity type impurityconcentration of the second SiC film.

This two-layer structure is (A) a two-layer structure of p⁻ (upperlayer)/n⁻ (lower layer), or (B) a two-layer structure of n⁻ (upperlayer)/p⁻ (lower layer).

In the case of the two-layer structure (A), a reverse bias voltage isapplied between the upper layer and the lower layer to form a depletionlayer in the ON-state. This depletion layer is formed regardless of theconductivity type of the channel region and the conductivity type of theSiC substrate.

In the case of the two-layer structure (B), a reverse bias voltage isapplied to the junction between the p layer (lower layer) and the n-typeSiC substrate to form a depletion layer in the ON-state when theconductivity type of the SiC substrate is the n type.

In the aforementioned case, the electric resistance is extremelyincreased due to formation of the depletion layer. This depletion layeris formed regardless of the conductivity type of the channel region.When the conductivity type of the SiC substrate is the p-type in theaforementioned case (B), no depletion layer is formed while both of theupper and lower layers of the aforementioned two-layer structure exhibitlow impurity concentrations and hence the electric resistance reaches ahigh value. In the aforementioned transverse JFET, the low concentrationvalue in the impurity concentration in the high-resistance region ispreferably set to not more than 1×10¹⁷ cm⁻³. When the low concentrationvalue of the first conductivity type or second conductivity typeimpurity in the aforementioned high-resistance region is set to not morethan 1×10¹⁷ cm⁻³, the electric resistance can be extremely increased dueto formation of the depletion layer, or the electric resistance can beincreased without forming the depletion layer.

In any of the aforementioned cases, high electric resistance is soensured that wattless currents flowing from the source and channelregions to the first SiC film can be suppressed for preventing reductionof the amplification factor.

In the transverse JFET according to the aforementioned third aspect ofthe present invention, the high-concentration impurity region and thechannel region are so formed that a depletion layer resulting from abuilt-in potential shuts off the channel region.

According to the aforementioned structure, normally off operation can becarried out. When the gate potential is set to zero with respect to thesource potential (ground potential in general), the channel region isdeenergized by the depletion layer extending from the junction betweenthe same and the high-concentration impurity region due to the built-inpotential. Therefore, the JFET enters an OFF-state with the gatepotential of zero. In order to bring the JFET into an ON-state, aprescribed plus potential may be applied. When no depletion layer growsas described above with the built-in potential, it follows that the JFETcarries out normally on operation. In other words, carriersunrestrictedly move in the channel region with the gate potential ofzero, while a minus potential is applied to the gate electrode forapplying a high reverse bias potential for attaining an OFF-state. Whenthe JFET carrying out normally on operation is loaded on a rotarymachine, power is supplied to the rotary machine also when a peripheralcircuit breaks down, and hence a counter control circuit must beprovided for preventing danger. When the normally on operation is set asdescribed above, the aforementioned control circuit is unnecessary.Whether to perform normally on operation or normally on operation can beset in response to the ratios of the impurity concentrations in thechannel region and the high-concentration impurity region, the length ofthe high-concentration impurity region, the thickness of the channelregion or the like. As hereinabove described, the normally off operationcan be readily attained as the ratio between the second conductivitytype impurity concentration in the high-concentration impurity regionand the first conductivity type impurity concentration in the channelregion is increased. In this description, the normally on operation isassumed unless the normally off operation is stated in particular.

In the transverse JFET according to the aforementioned third aspect ofthe present invention, the channel region can contain a firstconductivity type impurity of a higher concentration than the impurityconcentration of portions of the first conductivity type SiC filmlocated on both sides thereof, for example.

According to this structure, the depletion layer is formed to block thesections of the channel from both sides of the channel region to attainthe OFF-state so that the portion of this depletion layer withstands thevoltage, whereby ON-state resistance can be reduced without reducing thewithstand voltage of the transverse JFET. Therefore, this transverseJFET, consuming no power also when fed with a large current, can beapplied to a switching element having low loss and high withstandvoltage.

The transverse JFET according to the aforementioned third aspect of thepresent invention can have a conductor film arranged in contact with theface of the channel region, for example.

According to the aforementioned structure, influence exerted on thetransistor characteristics is small also when the impurity concentrationof the channel region or the thickness of the channel region isdispersed, and influence by dispersion of these factors substantiallycauses no problem. When the aforementioned conductor film is so arrangedthat side portions thereof are not in contact with portions of the firstconductivity type semiconductor layer holding the channel regiontherebetween in the OFF-state, for example, on the other hand, not onlythe channel region but also the conductor film is deenergized due to theaforementioned deenergization. Consequently, the OFF-state can bereadily implemented.

When the transverse JFET according to the aforementioned third aspect ofthe present invention has the conductor film, the length of theconductor film along the channel length direction can be renderedsmaller than a channel length, for example.

According to this structure, at least an end of the conductor film isinsulated from a side wall, whereby the JFET can be turned off bydeenergizing the channel region on the side where the depletion layer isinsulated.

When the transverse JFET according to the aforementioned third aspect ofthe present invention has the conductor film, the thickness of thechannel region can be rendered smaller than the width of a depletionlayer in the first conductivity type SiC film resulting from a built-inpotential on the junction between the second conductivity type SiC filmand the said first conductivity type SiC film formed on the secondconductivity type SiC film.

According to the aforementioned structure, a normally off JFET can beobtained and employed for controlling a rotary machine or the like withno countermeasure against breakdown of the gate circuit. Further, powerconsumption can be reduced in the ON-state, and influence by dispersionof the impurity concentration of the channel region or the like can alsobe avoided.

When the transverse JFET according to the aforementioned third aspect ofthe present invention has the conductor film, the conductor film can beformed by either a metal film or a semiconductor film containing ahigh-concentration impurity.

According to the aforementioned structure, a parallel bypass of lowresistance can be simply provided on the channel region with a metalfilm of low resistance. The metal film may be made of any material sofar as the same serves as an electrode material, while aluminum (Al) oran aluminum alloy is desirable in consideration of easiness of etchingand high conductivity.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view of a transverse JFET according to a firstembodiment of the present invention.

FIG. 2 is a sectional view of a transverse JFET according to a secondembodiment of the present invention.

FIG. 3 is a sectional view of a transverse JFET according to a thirdembodiment of the present invention.

FIG. 4 is a sectional view of a comparative JFET for the transverse JFETaccording to the third embodiment of the present invention.

FIG. 5 is a sectional view of another transverse JFET according to thethird embodiment of the present invention.

FIG. 6 is a sectional view of a transverse JFET according to a fourthembodiment of the present invention.

FIG. 7 is a sectional view of a stage forming an n⁺ SiC film andpatterning the same by RIE in an intermediate fabrication stage for thetransverse JFET shown in FIG. 6.

FIG. 8 is a sectional view of a stage forming a channel region by RIEafter the stage shown in FIG. 7.

FIG. 9 is a sectional view of a stage forming an Ni film for formingelectrodes after the stage shown in FIG. 8.

FIG. 10 is a sectional view of a transverse JFET according to a fifthembodiment of the present invention.

FIG. 11 is a sectional view of a transverse JFET according to a sixthembodiment of the present invention.

FIG. 12 is a sectional view of a stage forming an n⁺ SiC film andpatterning the same by RIE in an intermediate fabrication stage for thetransverse JFET shown in FIG. 11.

FIG. 13 is a sectional view of a stage forming a channel region by RIEafter the stage shown in FIG. 12.

FIG. 14 is a sectional view of a stage forming an Ni film for formingelectrodes after the stage shown in FIG. 13.

FIG. 15 is a sectional view of a transverse JFET according to a seventhembodiment of the present invention.

FIG. 16 is a sectional view of a transverse JFET according to an eighthembodiment of the present invention.

FIG. 17 is a sectional view of a stage forming an n⁺ SiC film andpatterning the same by RIE in an intermediate fabrication stage for thetransverse JFET shown in FIG. 16.

FIG. 18 is a sectional view of a stage forming a channel region by RIEand ion-implanting an impurity after the stage shown in FIG. 17.

FIG. 19 is a sectional view of a stage forming an Ni film for formingelectrodes after the stage shown in FIG. 18.

FIG. 20 is a sectional view of a transverse JFET according to a ninthembodiment of the present invention.

FIG. 21 is a sectional view of a transverse JFET according to a tenthembodiment of the present invention.

FIG. 22 illustrates the relation between an element breakdown voltageand W.

FIG. 23 is a sectional view of a transverse JFET according to aneleventh embodiment of the present invention.

FIG. 24 is a sectional view of a transverse JFET according to a twelfthembodiment of the present invention.

FIG. 25 is a model diagram illustrating an OFF-state in the transverseJFET shown in FIG. 24;

FIG. 26 is a sectional view of a transverse JFET according to athirteenth embodiment of the present invention.

FIG. 27 is a sectional view of a transverse JFET according to afourteenth embodiment of the present invention.

FIG. 28 is a sectional view of a transverse JFET according to afifteenth embodiment of the present invention.

FIG. 29 is a sectional view of a transverse JFET according to asixteenth embodiment of the present invention.

FIG. 30 is a sectional view of a transverse JFET according to aseventeenth embodiment of the present invention.

FIG. 31 is a sectional view of a transverse JFET according to aneighteenth embodiment of the present invention.

FIG. 32 is a sectional view of a transverse JFET according to anineteenth embodiment of the present invention.

FIG. 33 is a sectional view of a transverse JFET according to atwentieth embodiment of the present invention.

FIG. 34 is a sectional view of a conventional transverse JFET.

FIG. 35 is a sectional view of another conventional transverse JFET.

FIG. 36 is a sectional view of a stage forming an n-channel layer in anintermediate fabrication stage for the transverse JFET shown in FIG. 35.

FIG. 37 is a sectional view of a stage forming an Ni film defining afirst layer of a two-layer electrode after the stage shown in FIG. 36.

FIG. 38 is a sectional view of a stage forming an Al film defining asecond layer of the two-layer electrode after the stage shown in FIG.37.

FIG. 39 is a sectional view of a stage providing a trench between a gateregion and a central portion after the stage shown in FIG. 38.

BEST MODES FOR CARRYING OUT THE INVENTION

Embodiments of the present invention are now described with reference tothe drawings.

FIRST EMBODIMENT

FIG. 1 is a sectional view of a transverse JFET according to a firstembodiment of the present invention. A p-type SiC film 2 is formed on ann-type SiC substrate 1 n, and an n-type SiC film 3 reduced in thicknessin a portion of a channel region 11 is formed thereon. On the n-type SiCfilm, n⁺-type impurity layers defining a source region 22 and a drainregion 23 are formed on opposite sides of the channel region 11. Asource electrode 12 and a drain electrode 13 form ohmic contact with thesource region 22 and the drain region 23 respectively. According to thisembodiment, gate electrodes 14 are formed on a front or top surface ofthe substrate 1 with the source and drain regions 22 and 23 therebetweenin plane. The feature of the afore-mentioned structure resides in themultilayer structure of the n-type SiC substrate/(L) multilayerjunction/p-type SiC film/(G) gate junction/n-type SiC film having thechannel region.

(A) A normally on JFET can perform high-speed switching for high powerwith a high yield due to employment of the aforementioned structure. (B)On the other hand, a normally off JFET is so structured that thethickness of a depletion layer exceeds the thickness a of the channeldue to spreading of the width of the depletion layer toward the n-typeSiC film resulting from a built-in potential in the aforementioned p-njunction. Therefore, the n-type impurity concentration of the n-type SiCfilm 3 including the channel region is set to 1×10¹⁶ cm⁻³, and thethickness a of the channel is set to not more than 500 nm, for example.This operation of the normally off JFET is performed as follows:

(B-1): When the JFET is off, i.e., when the potentials of the gateelectrodes are zero, a diffusion voltage is applied to the gate junctionto form a depletion layer. In this junction, the impurity concentrationof the p-type SiC film is increased for suppressing the depletion layerin application of a reverse bias voltage to the (L) multilayer junction.Thus, the impurity concentration is set higher than the n-type impurityconcentration in the channel region as a matter of course, and hence thedepletion layer widely extends toward the channel region with a smallwidth of extension toward the p-type SiC film. Thus, the depletion layercan block only the channel region by adjusting the impurityconcentration. Consequently, the OFF-state is implemented.

(B-2): When the JFET is on, i.e., when the gate voltage is plus, aforward bias voltage is applied to the (G) gate junction, no depletionlayer is formed, and the ON-state is implemented. When the potentials ofthe gate electrodes are plus, a reverse bias voltage is applied to theaforementioned (L) multilayer junction. However, both of the p-typeimpurity concentration of the p-type SiC film and the n-type impurityconcentration of the n-type SiC substrate are so increased that thewidth of a depletion layer is small and a current flows due totunneling. As to the aforementioned high impurity concentrations, then-type impurity concentration of the n-type SiC substrate in is set toabout 1×10¹⁹ cm⁻³, and the p-type impurity concentration of the p-typeSiC film is set to about 1×10¹⁹ cm⁻³. Since the impurity concentrationsare increased as described above, the withstand voltage on the junctionmay be so reduced that withstand voltage disappears to allow a currentflow. Therefore, the depletion layer in the aforementioned junctionhardly influences on on-off action of the JFET.

According to the structure of the transverse JFET in the aforementionedfirst embodiment, a high-power JFET having a high switching speed can beprepared with a high yield by employing electrons having high mobilityas carriers in the channel region while employing an n-type SiCsubstrate having low defect density. The yield of the JFET according tothe aforementioned embodiment in a prototype stage was as follows: Forthe purpose of comparison, the yield of a conventional JFET is alsoshown.

Inventive Sample: preparation on an n-type SiC substrate (firstembodiment): yield 90%

Conventional Sample: preparation on a p-type SiC substrate: yield 10%

From the aforementioned results, it is understood that the yield of theJFET according to this embodiment is remarkably improved.

SECOND EMBODIMENT

FIG. 2 is a sectional view showing a transverse JFET according to asecond embodiment of the present invention. This embodiment isremarkably different from the JFET according to the first embodiment ina point that a gate electrode 14 is arranged on the back side of ann-type SiC substrate 1 n. Operation and functions relevant to theremaining parts are identical to the operation and functions shown inthe first embodiment. According to this embodiment, the gate electrode14 is arranged on the back side of the n-type SiC substrate, whereby achannel region 11 can be linearly and widely seen through from the gateelectrode 14 to the front face. Therefore, a signal applied to the gateelectrode is linearly and widely transmitted to the channel region,whereby the JFET can perform on-off action at a high speed. In otherwords, the JFET can implement a high-speed switching element. Further,the planar size is reduced in the JFET according to the secondembodiment as compared with the arrangement of the gate electrodes inthe first embodiment, to exhibit stereoscopic arrangement. Thus, thedegree of integration of the JFET can be improved.

THIRD EMBODIMENT

FIG. 3 is a sectional view showing a transverse JFET according to athird embodiment of the present invention. FIG. 4 is a sectional view ofa JFET to be compared therewith. According to this embodiment, an endface 31 of a p-type SiC film 2 and an end face 32 of an n-type SiC film3 formed thereon are so misaligned with each other that the former islocated inward beyond the latter in plane. Referring to FIG. 4, on theother hand, both end faces are formed as aligned end faces 30. In thiscase, the end faces 30 are so exposed to ions during RIE that crystalsmay be damaged when etched by RIE. In the case of the end face structureshown in FIG. 3, on the other hand, the end face of the n-type SiC filmis etched by first etching A, while the inner portion is etched andexposed by second etching B and hence this portion is exposed to an ionatmosphere for only a short period. Therefore, such a possibility thatcrystals around the end face 32 are damaged by ions is extremelyreduced. Thus, a JFET having excellent transistor characteristics can beobtained while ensuring a high yield.

While the JFET shown in FIG. 3 has a back gate structure, a JFET havinga structure arranging gate electrodes 14 on side portions of a channelis also an influential structure of the present invention. In otherwords, a JFET exhibiting a high yield can be obtained without damagingsurface crystals on end portions by employing the structure shown inFIG. 5.

FOURTH EMBODIMENT

FIG. 6 is a sectional view of a transverse JFET according to a fourthembodiment. Referring to FIG. 6, a p⁺-type SiC film 2 is formed on anSiC substrate 1. The SiC substrate 1 and the p⁺-type SiC film 2 may beeither of 6H or of 4H. An n-type SiC film 3 formed with a channel regionis formed on the aforementioned p⁺-type SiC film 2. The n-type SiC film3 is reduced in thickness at the center, for defining the channel region11. A source electrode 12 and a drain electrode 13 are formed on asource region and a drain region, which are n⁺-type SiC films 4 locatedabove both side portions of the channel respectively. Ends of thep⁺-type SiC film 2 are not covered with the upper n-type SiC film 3 buttwo gate electrodes 14 are formed on the uncovered relatively widesingle plane to hold the source electrode 12 and the drain electrode 13formed above the center therebetween. In other words, conductive pathsbetween the source and drain regions and the gate electrodes have noportions narrowly necked by trenches or the like partway but communicatewith each other with wide sections. The n-type impurity concentrationsof the source region and the drain region are set high to attain ohmiccontact with Ni or the like. The impurity concentrations of therespective regions are preferably set as follows, for example:

-   -   The channel region 11 and the n-type SiC film 3: n-type impurity        2×10¹⁷ cm⁻³    -   The source and drain regions (n⁺-type SiC films) 4: n-type        impurity>1×10¹⁹ cm⁻³    -   The p⁺-type SiC film 2: p-type impurity>1×10¹⁹ cm⁻³

As to the channel region, the thickness a, the length L and the width win a direction perpendicular to the plane of FIG. 6 can be decided inresponse to the size of the element. All of the source electrode 12 andthe source region 22, the drain electrode 13 and the drain region 23 andthe gate electrodes 14 and the p⁺-type SiC film 2 defining the gateregion are connection of high-concentration regions having impurityconcentrations exceeding 1×10¹⁹ cm⁻³ and metal films, and hence ohmiccontact can be formed by employing Ni as the material for the metalfilms, for example.

In order to attain an OFF-state, a reverse bias voltage is applied tothe gate electrodes 14 for extending a depletion layer from a p-njunction under the channel region 11 toward the channel region 11 andblocking the section of the channel region. In a broad way, gateresistance Rg is formed between the gate electrodes and the lower end ofthe center of the depletion layer, and the capacitance of the depletionlayer can be regarded as the gate capacitance Cg. In order to attain anON-state, the reverse bias may be canceled for eliminating the depletionlayer. In the ON-state, carriers flow from the source electrode towardthe drain electrode through the channel region 11. When repeating on-offaction, the aforementioned gate resistance Rg and the gate capacitanceCg can be regarded as serially connected, and a rise (fall) time isproportionate to RgCg, which is the time constant in a transientphenomenon of this circuit. Therefore, the rise (fall) time in switchingcan be reduced by reducing the gate resistance Rg.

When the structure of the transverse JFET shown in FIG. 6 is employed, aJFET having stable performance can be provided by improving withstandvoltage without increasing on-state resistance and reducing a switchingresponse time. This JFET, providing simple and easy fabrication stepsand hardly causing trouble such as reduction of the yield, can befabricated at a low cost as a result.

EXAMPLE CORRESPONDING TO FOURTH EMBODIMENT

A transverse JFET employing the structure shown in FIG. 6 wasfabricated. In the channel region 11, the channel length L was set to 10μm, the channel thickness a was set to 300 nm (0.3 μm), and the channelwidth w perpendicular to the plane of FIG. 6 was set to 700 μm. FIGS. 7to 9 are diagrams illustrating inventive steps corresponding to FIGS. 36to 39 illustrating the method of fabricating the conventional transverseJFET.

First, a p⁺-type SiC film is formed on a p-type SiC substrate by athickness of 1 μm, followed by formation of an n-type SiC film. Ann⁺-type SiC film is further formed thereon followed by etching by RIE,for patterning a region including source and drain regions. The centerof the portion including the source and drain regions is etched by RIEfor providing a trench thereby isolating the source region 22 and thedrain region 23 from each other (FIG. 8). Further, the gate electrodesare provided on the p⁺-type SiC film 2, while the source electrode 12and the drain electrode 13 are provided on the source region 22 and thedrain region 23 which are n⁺ impurity regions respectively (FIG. 9).Thereafter no etching step is provided for providing trenches in thep⁺-type SiC film 2. In the comparative transverse JFET, impurityconcentrations were not particularly increased in both of the sourceregion and the drain region but left at the concentration of 2×10¹⁷ cm⁻³of the n-type SiC film 3, as shown in FIG. 35. A transverse JFET settingthe depth of the trenches in the p-type SiC film shown in FIG. 35 to 0.7μm and setting the thickness of p-type SiC film remaining on the bottomportion to 0.3 Jim was also prototyped as comparative example.

Rise (fall) times in switching were measured as to both transverseJFETs. Table 1 shows results of measurement normalizing the rise time incomparative example to 1. TABLE 1 Rise (Fall) Ratio Transverse JFETStructure (trenched:1) Untrenched (Inventive Example) 0.33 Trenched(Comparative Example) 1

As shown in Table 1, it was possible to reduce the switching rise (fall)time to ⅓ by forming the p-type SiC film 2 as an untrenched smooth planeand forming the gate electrodes 14 thereon. Consequently, it has beenrendered possible to obtain a transverse JFET having a high withstandvoltage and low ON-state resistance and capable of high-speed switching.

FIFTH EMBODIMENT

FIG. 10 is a sectional view of a transverse JFET according to a fifthembodiment of the present invention. The impurity concentrations ofportions other than a gate electrode are identical to those of thetransverse JFET shown in FIG. 6. FIG. 10 is characterized in that thegate electrode 14 is formed over the back side of a p-type SiC substrate1. According to the structure shown in FIG. 10, ON- and OFF-states canbe implemented by the same manner of applying a gate voltage as that inFIG. 6. Further, gate resistance Rg can be further reduced, and a rise(fall) time in switching can consequently be reduced. A fabricationmethod is also simplified, and the yield can be improved.

SIXTH EMBODIMENT

FIG. 11 is a sectional view of a transverse JFET according to a sixthembodiment. Referring to FIG. 11, a p⁺-type SiC film 2 is formed on anSiC substrate 1. On the aforementioned p⁺-type SiC film 2, alow-concentration layer 7 containing an n-type impurity of a lowerconcentration than a channel region is interposed between an n-type SiCfilm and the p⁺-type SiC film 2 so that there is no portion where thesefilms 3 and 2 are in contact with each other. The channel region 11 isformed on the said low-concentration layer 7 at the center. A sourceelectrode 12 and a drain electrode 13 are formed on a source region anda drain region which are n⁺ SiC films 4 located above both sides of thechannel as viewed from the channel region respectively. Ends of thep⁺-type SiC film 2 are not covered with the upper n-type SiC film 3 buttwo gate electrodes 14 are formed on the uncovered relatively widesingle plane to hold the source electrode 12 and the drain electrode 13formed above the center therebetween. In other words, conductive pathsbetween the source and drain regions and the gate electrodes have noportions narrowly necked by trenches or the like partway but communicatewith each other with wide sections. The impurity concentrations of therespective regions are preferably set as follows, for example:

-   -   The channel region 11: n-type impurity 2×10¹⁷ cm⁻³    -   The source and drain regions (n⁺-type SiC films) 4: n-type        impurity>1×10¹⁹ cm⁻³    -   The low-concentration layer 7: n-type impurity<2×10¹⁷ cm⁻³    -   The p⁺-type SiC film 2: p-type impurity>1×10¹⁹ cm⁻³

As to the channel region, the thickness a, the length L and the width win a direction perpendicular to the plane of FIG. 11 can be decided inresponse to the size of the element. Except the portions of theelectrodes 12, 13 and 14, the face is covered with a protective film 5consisting of SiO₂. All of the source electrode 12 and the source region22, the drain electrode 13 and the drain region 23 and the gateelectrodes 14 and the p⁺-type SiC film 2 defining the gate region areconnection of high-concentration regions having impurity concentrationsexceeding 1×10¹⁹ cm⁻³ and metal films, and hence ohmic contact can beformed by employing Ni as the material for the metal films andperforming heat treatment, for example.

Referring to FIG. 11, a forward bias voltage is applied to the gateelectrodes in an ON-state, and no depletion layer is formed in thechannel region 11. Therefore, carriers flow through a path reaching thedrain region through the source region and the channel region. This pathhas no factor increasing ON-state resistance in particular, leading tono power consumption. When a reverse bias voltage is applied to the gateelectrodes 14, a depletion layer extends toward the channel region froma p-n junction under the channel region and finally completely blocksthe channel portion, for implementing an OFF-state. When no trenches areprovided in the p-type SiC film 2 as in the present invention, gateresistance is so small that the rise (fall) time is reduced inrepetition of this on-off action.

When the structure of the transverse JFET shown in FIG. 11 is employed,a JFET having stable performance can be provided by improving withstandvoltage without increasing on-state resistance and reducing a switchingresponse time. This JFET, providing simple and easy fabrication stepsand hardly causing trouble such as reduction of the yield, can befabricated at a low cost as a result.

EXAMPLE 1 CORRESPONDING TO SIXTH EMBODIMENT

A transverse JFET employing the structure shown in FIG. 11 wasfabricated. The structures of respective regions of portions excludingthe channel region 11 and the low-concentration layer 7 are as describedabove. In the channel region 11, the channel length L was set to 10 μm,the channel thickness a was set to 300 nm (0.3 μm), and the channelwidth w perpendicular to the plane of FIG. 11 was set to 700 μm. Theimpurity concentration of the low-concentration layer (n-impurity layer)was set to 1×10¹⁵ cm⁻³, and the thickness was set to 0.1 μm.

FIGS. 12 to 14 are diagrams illustrating a method of fabricating theinventive transverse JFET corresponding to FIGS. 36 to 39 illustratingthe method of fabricating the conventional transverse JFET. First, ap⁺-type SiC film 2 is formed on a p-type SiC substrate 1 followed byformation of a low-concentration n-type SiC film 7, and an n-type SiCfilm 3 is formed thereon. Further, an n⁺-type SiC film 4 is formedthereon, followed by etching by RIE, for patterning a region includingsource and drain regions (FIG. 12). The center of the portion includingthe source and drain regions is etched by RIE for providing a trenchthereby isolating the source region 22 and the drain region 23 from eachother (FIG. 13). Further, the gate electrodes are provided on thep⁺-type SiC film 2, while the source electrode 12 and the drainelectrode 13 are provided on the source region 22 and the drain region23 which are n⁺ impurity regions respectively (FIG. 14). Thereafter noetching step is provided for providing trenches in the p⁺-type SiC film2. A transverse JFET having the structure shown in FIG. 35 was alsoprepared for the purpose of comparison. In the comparative transverseJFET, impurity concentrations were not particularly increased in both ofthe source region and the drain region but left at the concentration of2×10¹⁷ cm⁻³ of the n-type SiC film 3. Table 2 shows results ofmeasurement of withstand voltages and ON-state resistance values as tothese two transverse JFETs. TABLE 2 Withstand ON-State VoltageResistance Transverse JFET Structure (V) (mΩ-cm²) With Low-ConcentrationLayer 250 8.7 (Inventive Example) With No Low-Concentration Layer 25010.0 (Comparative Example)

As shown in Table 2, it was possible to reduce the ON-state resistancefrom 10 mΩ·cm² to 8.7 mΩ·cm² while keeping a high withstand voltage of250 V.

EXAMPLE 2 CORRESPONDING TO SIXTH EMBODIMENT

The structure of the aforementioned transverse JFET according to thesixth embodiment was employed for measuring the rise (fall) time uponvoltage application as the index of a response speed of a switchingelement while varying only the p-type impurity concentration of thep-type SiC film. Ni films were employed for the electrodes for formingohmic contact between the p-type impurity region and the ohmic contact.Table 3 shows the results of measurement. TABLE 3 Impurity Concentrationof P-Type SiC Film (/cm³) Rise (Fall) Time (ns) 1 × 10¹⁸ 2000 1 × 10¹⁹200 1 × 10²⁰ 20 1 × 10²¹ 2

As shown in Table 3, the p-type impurity concentration and theaforementioned rise time are in inverse-proportional relation, and therise (fall) time tends to be reduced as the p-type impurityconcentration is increased.

SEVENTH EMBODIMENT

FIG. 15 is a sectional view of a transverse JFET according to a seventhembodiment of the present invention. FIG. 15 is characterized in that agate electrode is formed over the back side of a p-type SiC substrate.According to the structure shown in FIG. 15, gate resistance Rg can bereduced, and a rise (fall) time in switching can be reduced as a result.Further, a fabrication method is also rendered simple and easy, forimproving the yield.

EIGHTH EMBODIMENT

FIG. 16 is a sectional view of a transverse JFET according to an eighthembodiment of the present invention. Referring to FIG. 16, a 6H-p⁺-typeSiC film 2 is formed on a 6H—SiC substrate 1. A 4H-type substrate can beemployed in place of the 6H-type substrate, as a matter of course. “6H-”or “4H-” is omitted in the following description. Referring to FIG. 16,a channel region 11 contains an n-type impurity in a higherconcentration than the impurity concentration of portions of an n-typeSiC film 3 located on both sides thereof. A source electrode 12 and adrain electrode 13 are formed on a source region and a drain regionwhich are n⁺ SiC films 4 located above both sides of the channel asviewed from the channel region 11 respectively. Ends of the p⁺-type SiCfilm 2 are not covered with the upper n-type SiC film 3 but two gateelectrodes 14 are formed on the uncovered relatively wide single planeto hold the source electrode 12 and the drain electrode 13 formed abovethe center therebetween. In other words, conductive paths between thesource and drain regions and the gate electrodes have no portionsnarrowly necked by trenches or the like partway but communicate witheach other with wide sections. The impurity concentrations of therespective regions are set as follows, for example:

-   -   The channel region 11: n-type impurity>1×10¹⁸ cm⁻³    -   The portions of the n-type SiC film 3 located on both sides of        the channel region: n-type impurity 2×10¹⁷ cm⁻³    -   The source and drain regions (n⁺-type SiC films) 4: n-type        impurity>1×10¹⁹ cm⁻³    -   The p-type SiC film 2: p-type impurity>1×10¹⁹ cm⁻³

As to the channel region, the thickness a, the length L and the width win a direction perpendicular to the plane of FIG. 16 can be decided inresponse to the size of the element. The source electrode 12 and thesource region 22 as well as the drain electrode 13 and the drain region23 are connection of high-concentration regions having impurityconcentrations exceeding 1×10¹⁹ cm⁻³ and metal films, and hence ohmiccontact can be formed by employing Ni as the material for the metalfilms, for example. Further, connection between the gate electrodes 14and the p-type SiC film 2 defining the gate region is also connection ofhigh-concentration regions having impurity concentrations exceeding1×10¹⁹ cm⁻³ and a metal film, and hence ohmic contact can be formed byemploying Ni as the material for the metal film and performing heattreatment, for example.

In an ON-state of this transverse JFET, carriers flow through a pathreaching the drain region 23 from the source electrode 12 through thesource region 22 and the channel region 11. In this path, the channelregion has a high impurity concentration despite the small sectionalarea, whereby resistance can be reduced, ON-state resistance is reduced,and power consumption can be reduced. Also when a high current is fed,therefore, power loss is so small that heat generation can besuppressed. In order to attain an OFF-state, a reverse bias voltage isapplied to the gate electrodes 14 for forming a depletion layer on ann-type SiC film side of a p-n junction. This depletion layer remarkablydevelops on both sides of the channel region 11 and grows into thechannel to block the section of the path of the channel region as thereverse bias voltage is increased. The OFF-state is attained when thedepletion layer blocks the section of the path of the channel region.

When this structure of the transverse JFET is employed, a JFET havingstable performance can be provided by improving withstand voltagewithout increasing ON-state resistance and reducing the switchingresponse time. Therefore, the JFET can be employed as a high-powerhigh-speed switching element having low loss. This JFET, providingsimple and easy fabrication steps and hardly causing trouble such asreduction of the yield, can be fabricated at a low cost as a result.

EXAMPLE CORRESPONDING TO EIGHTH EMBODIMENT

A transverse JFET employing the structure shown in FIG. 16 wasfabricated. FIGS. 17 to 19 are diagrams illustrating steps correspondingto FIGS. 36 to 39 illustrating the method of fabricating theconventional transverse JFET. First, a p⁺-type SiC film is formed on ap-type SiC substrate, followed by formation of an n-type SiC film. Theimpurity concentration of this n-type SiC film 3 was set to 1.66×10¹⁷cm⁻³. An n⁺-type SiC film is further formed thereon followed by etchingby RIE, for patterning a region including source and drain regions (FIG.17). Then, the center of the portion including the source and drainregions is etched by RIE for providing a trench thereby isolating thesource region 22 and the drain region 23 from each other. A channelregion 11 formed under the bottom of this trench is doped with an n-typeimpurity by ion implantation (FIG. 18). The n-type impurityconcentration of the channel region 11 was set to 1.36×10¹⁸ cm⁻³. Thechannel length L was set to 8 μm, the channel thickness a was set to 214nm (0.214 μm), and the width w of a direction perpendicular to thefigures was set to 0.72 mm. Further, the gate electrodes are provided onthe p⁺-type SiC film 2, while the source electrode 12 and the drainelectrode 13 are provided on the source region 22 and the drain region23 which are n⁺ impurity regions respectively (FIG. 19). Thereafter noetching step is provided for providing trenches in the p⁺-type SiC film2. In a comparative transverse JFET, impurity concentrations were notparticularly increased in both of the source region and the drain regionbut left at the concentration of 1.66×10¹⁷ cm⁻³ of the n-type SiC film3, as shown in FIG. 35. A channel was shaped identically to that of theaforementioned transverse JFET according to the present invention.Withstand voltages and ON-state resistance values were measured as toboth transverse JFETs. Table 4 shows the results of measurement in bothJFETs. TABLE 4 ON-State Resistance (With Withstand Voltage Applicationof 1 V) Channel (V) (mΩ-cm²) High-Impurity 155 0.93 ConcentrationChannel (Inventive Example) Conventional Channel 155 2.20 (ComparativeExample)

As shown in Table 4, it was possible to reduce the ON-state resistancefrom 2.20 mΩ cm² to 0.93 mΩ·cm² while keeping a high withstand voltageof 155 V.

NINTH EMBODIMENT

FIG. 20 is a sectional view of a transverse JFET according to a ninthembodiment of the present invention. The impurity concentrations ofportions other than a gate electrode are identical to those in thetransverse JFET shown in FIG. 16. FIG. 20 is characterized in that thegate electrode 14 is formed over the back side of a p-type SiC substrate1. According to the structure shown in FIG. 20, ON- and OFF-states canbe implemented by the same manner of applying a gate voltage as that inFIG. 16. Further, gate resistance Rg can be more reduced, whereby a rise(fall) time in switching can be reduced as a result. A fabricationmethod is also simplified, and improvement of the yield can be attained.

TENTH EMBODIMENT

FIG. 21 is a sectional view of a transverse JFET according to a tenthembodiment of the present invention. Referring to FIG. 21, the thicknessa of a channel region 21 is rendered smaller than the width of adepletion layer formed on the side of an n⁻ layer due to a built-inpotential (about 2 V to 3 V) of a p-n junction. The “width” of thejunction part indicates the thickness in FIG. 21. More specifically, thethickness a of the channel region is not more than 500 nm when theimpurity concentration of the n⁻ layer is set to 1×10¹⁶ cm⁻³. Theimpurity concentration n of the channel region is preferably set largerthan the concentration n⁻ of the n⁻ layer. In order to implement anON-state in the transverse JFET shown in FIG. 21, a positive potentialhigher than a source potential is applied to gate electrodes. The p-njunction is rendered conductive if the gate potential is increasedbeyond the built-in potential, and hence it is meaningless to increasethe gate potential beyond the built-in potential. In other words, thegate potential may be set to zero in an OFF-state, while the gatepotential may be set to a positive level of about 3 V in the ON-state.

Withstand voltage design as to the transverse JFET shown in FIG. 21 isnow described. The JFET is designed to have a withstand voltage of 200V, and the thickness H of an n-type SiC film 3 shown in FIG. 21 is setto 900 nm. At this time, the withstand voltage is 210 to 220 V, reliablyexceeding 200 V, on the basis of the relation between H and thewithstand voltage shown in FIG. 22. When H is 900 nm, the thickness a ofthe channel region can be set to 500 nm, and the impurity concentrationof the n⁻ layer providing the thickness of the depletion layer largerthan this thickness a resulting from the built-in potential is not morethan about 1×10¹⁶ cm⁻³, as described above. The impurity concentration nof the channel region 11 can be set to 3.8×10¹⁷ cm⁻³, which is higherthan the impurity concentration of the n⁻ layer. Thus, a normally offtransverse JFET can be obtained while ensuring withstand voltage.Therefore, a normally off state can be implemented, power consumptioncan be reduced and a rotary machine or the like can be controlled bythis transverse JFET with no countermeasure against breakdown of a gatecircuit.

ELEVENTH EMBODIMENT

FIG. 23 is a sectional view of a transverse JFET according to aneleventh embodiment of the present invention. Referring to FIG. 23, ann-type SiC film is formed by two layers of lower n⁻ layers 3 a and uppern₁ layers 3 b on both sides of a channel region 21. In order toimplement withstand voltage, high-speed on-off action and a normally offstate, the concentration n₁ of the upper layers and the concentration n₂of the channel region 11 are preferably higher than n-, and n₂ ispreferably higher than n⁻. Also according to this structure, a normallyoff transverse JFET can be obtained similarly to the tenth embodimentwhile ensuring high-speed on-off action and withstand voltage at a highlevel.

In order to attain a withstand voltage of 200 V, the thickness H of theaforementioned two layers (n⁻ layer/n₁ layer) is set to 1200 nm, whilesetting the impurity concentrations as follows respectively: Thewithstand voltage of 200 V can be ensured for obtaining a normally offtransverse JFET carrying out high-speed on-off action by setting theconcentration n₁ of the upper n layers to 1×10¹⁷ cm⁻³, the concentrationn⁻ of the lower n layers to 1×10¹⁶ cm⁻³, the concentration n₂ of thechannel region to 3.8×10¹⁷ cm⁻³ and the thickness a of the channelregion to 500 nm.

TWELFTH EMBODIMENT

FIG. 24 is a sectional view showing a transverse JFET according to atwelfth embodiment of the present invention. Referring to FIG. 24, ap-type SiC film 2 is formed on an SiC substrate 1, and an n-type SiCfilm 3 having a portion of a channel region 11 reduced in thickness isformed thereon. On portions of the n-type SiC film 3 located on bothsides of the channel region 11, n⁺-type SiC films 22 and 23 for definingsource and drain regions are formed, and source and drain electrodes 12and 13 are further formed on the respective regions. Two gate electrodes14 are formed on the p-type SiC film in plane on opposite outer sides ofthe source and drain regions. The most significant feature of thisembodiment resides in that an aluminum film 17 is formed on the channelregion. The sectional length of this aluminum film is smaller than achannel length L, and the aluminum film is included in the channelregion in plane. In other words, the aluminum film 17 is not in contactwith walls of the n-type SiC film 3 on both sides of the channel region11.

Operation of this JFET is now described. In an ON-state, carriers flowthrough the channel region 11 along the substrate face. When thealuminum layer 17 is arranged on the channel region at this time, acurrent flows through a parallel circuit formed by the channel region 11and the aluminum film 17. When the electric resistance of the aluminumfilm is lower by 1 order, for example, as compared with the electricresistance of the channel region, the current flowing through thealuminum film 17 is higher substantially by 1 order than the currentflowing through the channel region. Consequently, the current flowing inthe semiconductor is substantially ignorable, and transistorcharacteristics hardly depend on the impurity concentration of thechannel region or the thickness a of the channel region. Consequently,the channel region may not be doped with an impurity of a highconcentration for reducing the electric resistance thereof but othertransistor characteristics can be ensured with no dispersion whilekeeping high withstand voltage.

In an OFF-state, on the other hand, a negative potential is applied tothe gate electrodes 14 shown in FIG. 25. Therefore, a depletion layer isformed on the junction between the p-type SiC film 2 and the n-type SiCfilm 3, and the width of the depletion layer spreads toward a sidehaving a lower impurity concentration substantially in inverseproportion to the impurity concentration as the absolute value of thenegative potential is increased. When the forward end of the width ofthe depletion layer exceeds the thickness a of the channel region 11,the depletion layer blocks the channel region and hinders passage of thecarriers. The aluminum film 17 is not in contact with the walls on bothsides of the channel region 11 as described above, and hence theOFF-state is implemented when the aforementioned forward end of thewidth of the depletion layer exceeds the thickness a of the channelregion.

EXAMPLE CORRESPONDING TO TWELFTH EMBODIMENT

The JFET shown in the twelfth embodiment of FIG. 24 was prototyped formeasuring channel resistance upon application of 1 V. This JFET wasprepared as an element having a withstand voltage of 100 V. The impurityconcentration of the n-type SiC films 3 and 4 including the channelregion was set to 4.0×10¹⁷ cm⁻³, the channel length L was set to 10000nm (10 μm), and the thickness a of the channel region was set to 230 nm.TABLE 5 Channel Resistance (With Application of 1 V) ClassificationUnit: mΩ cm² Inventive Example 1.6 Conventional Example 7.8

According to the results shown in Table 5, the channel resistance of aconventional JFET (JFET prepared by removing the aluminum film from theJFET shown in FIG. 24) having no metal film on a channel region was 7.8mΩcm². On the other hand, the channel resistance of the JFET (inventivesample) according to the twelfth embodiment comprising the aluminum filmwas remarkably reduced to 1.6 mΩcm². Therefore, it has been recognizedthat the channel resistance is remarkably reduced due to the inventivesample. Thus, it was possible to obtain a JFET having small dispersionbetween elements with no influence by fluctuation of the impurityconcentration of the channel region or the thickness of the channelregion.

THIRTEENTH EMBODIMENT

The transverse JFET according to the aforementioned twelfth embodimentshown in FIGS. 24 and 25 implements a normally on state where thecurrent flows through the channel region 4 when the gate voltage iszero. A normally on JFET, having a possibility of not stopping rotationwhen employed for controlling a rotary machine or the like and a gatecircuit is broken down, must comprise a mechanism for dealing withbreakdown of the gate circuit. It is troublesome to comprise such amechanism, and hence a normally off JFET is desirable. The normally offJFET is described with reference to a second embodiment. As shown inFIG. 26, the maximum feature of this embodiment resides in the followingpoint: The width of a depletion layer resulting from a built-inpotential of a p-n₂ junction, i.e., a depletion layer formed when a gatepotential is zero, is rendered larger than the thickness a of a channelregion. When (a) setting a concentration n₂ to 1×10¹⁶ cm⁻³ and (b)setting the thickness a of the channel region to not more than about 500nm, for example, the width of the depletion layer resulting from thebuilt-in potential exceeds the thickness a of the channel region, sothat the normally off JFET can be obtained.

When employing the aforementioned structure, a normally off JFET neitherreducing withstand voltage nor dispersing characteristics due tofluctuation of the channel concentration or the like can be implemented.Consequently, the JFET can be applied to a controller for a large-sizedrotary machine or the like without providing a mechanism for dealingwith breakdown of a gate circuit.

FOURTEENTH EMBODIMENT

FIG. 27 is a sectional view showing a transverse JFET according to afourteenth embodiment of the present invention. On a p⁺-type SiCsubstrate, p-type epitaxial SiC films 2 a, 2 b and 2 c adjusted inconcentration in response to regions are formed. A p⁺ SiC layer 2 a isformed on a high-concentration impurity region located under a channelregion 11, and p SiC layers 2 b and 2 c of high electric resistancelayers are arranged on both sides thereof. An n-type epitaxial SiC filmis formed thereon, and a trench 19 defines portions connecting thechannel region 11 and source and drain regions 22 and 23.High-concentration n⁻ source and drain regions 22 and 23 are formed onthese portions for implementing ohmic contact respectively, and sourceand drain electrodes 12 and 13 are provided thereon. A gate electrode 14is provided on the back side of the high-concentration p⁺-type SiCsubstrate, for forming a back gate structure. The gate electrode isprovided on the SiC substrate containing an impurity in highconcentration, since ohmic contact can be obtained. However, the gateelectrode may not necessarily have the back gate structure, but suchgate electrodes may alternatively be provided on portions of the SiCsubstrate 1 located on sides of the p SiC layers 2 b and 2 c of highelectric resistance layers. When the back gate structure is employed, apower device improved in degree of integration can be formed. When thegate electrodes are provided on the portions of the SiC substrate 1located on sides of the p⁻ SiC layers 2 b and 2 c of high electricresistance layers, on the other hand, the JFET can be advantageouslycompleted while forming respective portions on a single face in afabrication flow for a semiconductor device such as an LSI chip.

FIG. 27 is characterized in that the length of the p⁺ SiC layer 2 a isrendered smaller than the length of the channel region, and although theimpurity concentration is high, electric resistance of thishigh-concentration impurity region is increased by reducing thesectional area in the thickness direction. Referring to FIG. 27, it isassumed that the direction perpendicular to the plane of the figure isthe width direction of the transverse JFET, the longitudinal directionof the channel is the length, and the direction orthogonal to the planeof lamination is the thickness direction.

The aforementioned p⁺ SiC layer 2 a of the high-concentration impurityregion may not be provided under the channel region 11 but may belocated on a portion close to the source region 22. The p⁻ SiC layers 2b and 2 c of the high-resistance regions located on both sides thereofhave a low impurity concentration and high resistance, and hence thequantities of currents leaking from the source and channel regions andpenetrating into the p SiC layers 2 b and 2 c are reduced.

When the p⁺ SiC layer 2 a is formed by ion implantation, the minimumwidth can be set to about 1 μm. Therefore, the resistance of this p⁺ SiClayer 2 a reaches a large value.

When providing the p⁺ SiC layer 2 a small and reducing the concentrationon both sides thereof as described above a channel leakage currentfollowing a forward bias can be suppressed as compared with the priorart. Consequently, reduction of the amplification factor in an ON-statecan be prevented.

FIFTEENTH EMBODIMENT

FIG. 28 is a sectional view showing a transverse JFET according to afifteenth embodiment of the present invention. Structures different fromthose of the transverse JFET shown in FIG. 27 are only high-resistanceregions under source, channel and drain regions. These high-resistanceregions are provided as n⁻ SiC layers 2 b and 2 c on both sides of a p⁺SiC layer 2 a. The n-type impurity concentration of these layers 2 b and2 c is reduced, as a matter of course.

In the case of the aforementioned structure, the resistance of the n⁻SiC layers 2 b and 2 c on both sides of the p⁺ SiC layer 2 a is largesimilarly to the fourteenth embodiment. Therefore, currents leaking fromthe source and channel regions to a first SiC film are suppressed andreduction of the amplification factor can be prevented, similarly to thefourteenth embodiment.

SIXTEENTH EMBODIMENT

FIG. 29 is a sectional view showing a transverse JFET according to asixteenth embodiment of the present invention. Structures different fromthose of the transverse JFET shown in FIG. 27 are only high-resistanceregions under source, channel and drain regions. These high-resistanceregions are provided as two-stage layers, i.e., p⁻ SiC layers 21 b and21 c/n⁻ SiC layers 20 b and 20 c on both sides of a p⁺ SiC layer 2 a. Areverse bias voltage is applied to p⁻-n⁻ junction planes of thehigh-resistance regions provided on both sides in an ON-state.Therefore, depletion layers are formed on the p⁻-n⁻ junction planesshown by arrows in FIG. 29. Thus, resistance against currents leakingfrom source and channel regions is extremely increased, and theaforementioned leakage currents are remarkably suppressed. The casewhere depletion layers are formed on peripheral regions other than ahigh-concentration impurity region of a first SiC film so that theelectric resistance of high-resistance regions is extremely increased inan ON-state as in this embodiment is most desirable.

SEVENTEENTH EMBODIMENT

FIG. 30 is a sectional view showing a transverse JFET according to aseventeenth embodiment of the present invention. The structure of thetransverse JFET shown in FIG. 30 is different from that of thetransverse JFET according to the fourteenth embodiment shown in FIG. 27only in a point that an n⁺ SiC substrate 1 is employed as the substrate.In other words, a p⁺ SiC layer 2 a of a high-concentration impurityregion is provided with the smallest possible length, similarly to thefourteenth embodiment.

The n⁺ SiC substrate 1 is employed as the substrate, whereby a reversebias voltage is applied to junction planes between the substrate 1 andp⁻ SiC layers 2 b and 2 c in an ON-state, and hence depletion layersgrow on the p⁻ SiC layers 2 b and 2 c. According to this embodiment,therefore, resistance is extremely increased due to formation of thedepletion layers on both sides of the p⁺ SiC layer 2 a of thehigh-concentration impurity region, so that currents leaking from sourceand channel regions to a first SiC film can be remarkably suppressed.Also in the seventeenth embodiment, a case where depletion layers areformed on high-resistance layers in an ON-state is most desirable.

EIGHTEENTH EMBODIMENT

FIG. 31 is a sectional view showing a transverse JFET according to aneighteenth embodiment of the present invention. The structure of thetransverse JFET shown in FIG. 31 is different from that of thetransverse JFET according to the fifteenth embodiment shown in FIG. 28only in a point that an n⁺ SiC substrate 1 is employed as the substrate.In other words, a p⁺ SiC layer 2 a of a high-concentration impurityregion is provided with the smallest possible length, similarly to thefifteenth embodiment. A principle suppressing currents leaking to afirst SiC film is also identical to that in the transverse JFET shown inFIG. 28, and hence description is omitted.

NINETEENTH EMBODIMENT

FIG. 32 is a sectional view showing a transverse JFET according to anineteenth embodiment of the present invention. The structure of thetransverse JFET shown in FIG. 32 is different from that of thetransverse JFET according to the sixteenth embodiment shown in FIG. 29only in a point that an n⁺ SiC substrate 1 is employed as the substrate.In other words, a p⁺ SiC layer 2 a of a high-concentration impurityregion is provided with the smallest possible length, similarly to thesixteenth embodiment. A principle suppressing currents leaking to afirst SiC film as well as a principle forming depletion layers are alsoidentical to those in the transverse JFET shown in FIG. 29, and hencedescription is omitted.

TWENTIETH EMBODIMENT

FIG. 33 is a sectional view showing a transverse JFET according to atwentieth embodiment of the present invention. Each of theaforementioned fourteenth to nineteenth embodiments has been assumed tocarry out normally on operation. In other words, it has been assumedthat a gate voltage is set to zero or slightly plus with respect to asource potential (ground potential in general) for attaining anON-state. In order to attain an OFF-state, therefore, a prescribed minusvoltage must be applied to a gate. However, an additional controlcircuit must be provided on a normally on JFET as a countermeasureagainst breakdown, and a transverse JFET carrying out normally offoperation is more preferable. In other words, it is preferable that adepletion layer grows to a channel region from a p⁺ SiC layer 2 a toblock the channel region when the gate voltage is zero, for attaining anON-state when the gate voltage is set to a prescribed plus level.

Referring to FIG. 33, the concentration of a p⁺ SiC layer 2 of ahigh-concentration impurity region is increased and the n-type impurityconcentration of a channel region 11 is reduced so that a depletionlayer 18 blocks the channel region 11 with a gate voltage of zero, i.e.,with a built-in potential. Therefore, the JFET is turned off with thegate voltage of zero, and no control circuit may be provided for dealingwith breakdown of a gate circuit. The structure of the transverse JFETshown in FIG. 33 is identical to the structure of the transverse JFETshown in FIG. 27 except the aforementioned portion, and hence amechanism of suppressing currents leaking from source and channelregions to a first SiC film is identical to that described in thefourteenth embodiment.

While embodiments and Examples of the present invention have beendescribed in the above, the embodiments and Examples of the presentinvention disclosed in the above are only illustrative, and the scope ofthe present invention is not restricted to these embodiments andExamples of the present invention. The scope of the present invention isshown by description of the scope of claim for patent, and includes allmodifications within the meaning and range equivalent to the descriptionof the scope of claim for patent.

According to the present invention, it is possible to obtain a JFET ofSiC employing an n-type SiC substrate bringing a high yield andcomprising a channel region employing electrons having high mobility.Further, it is possible to provide a transverse JFET of uniform qualitysuitable for a high-power semiconductor switching element excellent inwithstand voltage and high-speed property. Further it is possible toobtain a transverse JFET capable of suppressing currents leaking fromsource and channel regions to a first SiC film and preventing reductionof the amplification factor.

1. A transverse junction field effect transistor comprising: an n⁺-typeSiC substrate; a p-type SiC film formed on a front face of said SiCsubstrate; an n-type SiC film formed on said p-type SiC film; a channelregion formed in said n-type SiC film; a source region and a drainregion, respectively comprising films consisting of n-type SiC formed onsaid n-type SiC film respectively separately on opposite sides of saidchannel region; and a gate electrode arranged in one of the followingarrangements: on a back side of said SiC substrate, or on and surroundedby a flat region of said front face of said SiC substrate with said flatregion extending laterally beyond said gate electrode, or on andsurrounded by a flat region of said p-type SiC film with said flatregion extending laterally beyond said gate electrode.
 2. The transversejunction field effect transistor according to claim 1, wherein: saidp-type SiC film (2) is formed on said front face of said SiC substrate;said n-type SiC film (3), including said channel region (11), is formedon said p-type SiC film; and said gate electrode (14) is provided incontact with said SiC substrate.
 3. The transverse junction field effecttransistor according to claim 2, wherein a region of said p-type SiCfilm (2) corresponds to a region of said n-type SiC film (3) as viewedin plan.
 4. The transverse junction field effect transistor according toclaim 2, wherein said gate electrode (14) is arranged on said front faceof said SiC substrate (1 n) in a vicinity of an end of said p-type SiCfilm (2).
 5. The transverse junction field effect transistor accordingto claim 2, wherein said gate electrode (14) is arranged in a back gatestructure on said back side of said SiC substrate (1 n) opposite saidfront face.
 6. The transverse junction field effect transistor accordingto claim 2, wherein a thickness (a) of said channel region (11) issmaller than a width of a depletion layer in said n-type SiC filmresulting from a: built-in potential on a junction between said p-typeSiC film (2) and said n-type SiC film (3) formed on said p-type SiCfilm.
 7. The transverse junction field effect transistor according toclaim 2, further comprising a low-concentration n-type SiC film (7),arranged in contact between said p-type SiC film (2) and said n-type SiCfilm (3), containing an n-type impurity of a lower concentration than ann-type impurity concentration of said channel region (11).
 8. Thetransverse junction field effect transistor according to claim 2,wherein said channel region (11) contains an n-type impurity of a higherconcentration than an impurity concentration of portions of said n-typeSiC film located on both sides thereof.
 9. The transverse junction fieldeffect transistor according to claim 2, further comprising a conductorfilm (17) arranged in contact with a surface of said channel region(11).
 10. The transverse junction field effect transistor according toclaim 9, wherein a length of said conductor film (17) along a channellength direction is smaller than a channel length (L) of said channelregion in said channel length direction.
 11. The transverse junctionfield effect transistor according to claim 9, wherein a thickness (a) ofsaid channel region (11) is smaller than a width of a depletion layer insaid n-type SiC film resulting from a built-in potential on a junctionbetween said p-type SiC film (2) and said n-type SiC film (3) formed onsaid p-type SiC film.
 12. The transverse junction field effecttransistor according to claim 9, wherein said conductor film (17) iseither a metal film or a semiconductor film containing ahigh-concentration impurity.
 13. The transverse junction field effecttransistor according to claim 2, wherein said SiC substrate (1) is a6H—SiC substrate, and both of said p-type SiC film (2) and said n-typeSiC film (3) are made of 6H—SiC.
 14. The transverse junction fieldeffect transistor according to claim 2, further comprising a bufferlayer of 4H—SiC, wherein said SiC substrate is a 6H—SiC substrate, bothof said p-type SiC film (2) and said n-type SiC film (3) are made of4H—SiC, and said p-type SiC film (2) consisting of 4H—SiC is formed onsaid 6H—SiC substrate with said buffer layer of 4H—SiC therebetween. 15.The transverse junction field effect transistor according to claim 2,wherein said SiC substrate (1) is a 4H—SiC substrate, and both of saidp-type SiC film (2) and said n-type SiC film (3) are made of 4H—SiC. 16.The transverse junction field effect transistor according to claim 2,further comprising a buffer layer of 6H—SiC, wherein said SiC substrateis a 4H—SiC substrate, both of said p-type SiC film (2) and said n-typeSiC film (3) are made of 6H—SiC, and said p-type SiC film consisting of6H—SiC is formed on said 4H—SiC substrate with said buffer layer of6H—SiC therebetween.
 17. The transverse junction field effect transistoraccording to claim 1, wherein said channel region (11) is formed byreducing a thickness of said n-type SiC film.
 18. The transversejunction field effect transistor according to claim 17, wherein saidp-type SiC film (2) has an untrenched flat face, and said gate electrode(14) comprises two gate electrode elements formed on said flat face ofsaid p-type SiC film (2) which forms said flat region of said p-type SiCfilm.
 19. The transverse junction field effect transistor according toclaim 17, wherein said gate electrode (14) is formed in a back gatestructure provided on a flat region of said back side of said SiCsubstrate.
 20. The transverse junction field effect transistor accordingto claim 17, further comprising a low-concentration n-type SiC film (7),arranged in contact between said p-type SiC film (2) and said n-type SiCfilm (3), containing an n-type impurity of a lower concentration than ann-type impurity concentration of said channel region (11).
 21. Thetransverse junction field effect transistor according to claim 17,wherein said channel region (11) contains an n-type impurity of a higherconcentration than an impurity concentration of portions of said n-typeSiC film located on both sides thereof.
 22. The transverse junctionfield effect transistor according to claim 20, wherein said channelregion (11) contains an n-type impurity of a higher concentration thanan impurity concentration of portions of said n-type SiC film located onboth sides thereof.
 23. The transverse junction field effect transistoraccording to claim 17, wherein a thickness (a) of said channel region(11) is smaller than a width of a depletion layer in said n-type SiCfilm resulting from a built-in potential on a junction between saidp-type SiC film (2) and said n-type SiC film (3) formed on said p-typeSiC film.
 24. The transverse junction field effect transistor accordingto claim 21, wherein a thickness (a) of said channel region (11) issmaller than a width of a depletion layer in said n-type SiC filmresulting from a built-in potential on a junction between said p-typeSiC film (2) and said n-type SiC film (3) formed on said p-type SiCfilm.
 25. The transverse junction field effect transistor according toclaim 17, further comprising a conductor film (17) arranged in contactwith a surface of said channel region (11).
 26. The transverse junctionfield effect transistor according to claim 25, wherein a length of saidconductor film (17) along a channel length direction is smaller than achannel length (L) of said channel region in said channel lengthdirection.
 27. The transverse junction field effect transistor accordingto claim 25, wherein a thickness (a) of said channel region (11) issmaller than a width of a depletion layer in said n-type SiC filmresulting from a built-in potential on a junction between said p-typeSiC film (2) and said n-type SiC film (3) formed on said p-type SiCfilm.
 28. The transverse junction field effect transistor according toclaim 25, wherein said conductor film (17) is either a metal film or asemiconductor film containing a high-concentration impurity.
 29. Thetransverse junction field effect transistor according to claim 17,wherein said source region and said drain region (22, 23) contain ann-type impurity of a higher concentration than an impurity concentrationof portions of said n-type SiC film (3) located on both sides of saidchannel region (11).
 30. The transverse junction field effect transistoraccording to claim 17, wherein an impurity concentration of said p-typeSiC film (2) exceeds 10¹⁹ cm⁻³.
 31. The transverse junction field effecttransistor according to claim 17, further comprising a source electrode(12) formed on said source region (22), and a drain electrode (13)formed on said drain region (23), wherein said source electrode, saiddrain electrode and said gate electrode are made of metals coming intoohmic contact with SiC, containing impurities, in contact with therespective electrodes.
 32. The transverse junction field effecttransistor according to claim 31, further comprising an insulating film(5) covering a surface portion excluding said source electrode (12),said drain electrode (13) and said gate electrode (14).
 33. Thetransverse junction field effect transistor according to claim 17,wherein said SiC substrate (1) is a 6H—SiC substrate, and both of saidp-type SiC film (2) and said n-type SiC film (3) are made of 6H—SiC. 34.The transverse junction field effect transistor according to claim 17,further comprising a buffer layer of 4H—SiC, wherein said SiC substrateis a 6H—SiC substrate, both of said p-type SiC film (2) and said n-typeSiC film (3) are made of 4H—SiC, and said p-type SiC film (2) consistingof 4H—SiC is formed on said 6H—SiC substrate with said buffer layer of4H—SiC therebetween.
 35. The transverse junction field effect transistoraccording to claim 17, wherein said SiC substrate (1) is a 4H—SiCsubstrate, and both of said p-type SiC film (2) and said n-type SiC film(3) are made of 4H—SiC.
 36. The transverse junction field effecttransistor according to claim 17, further comprising a buffer layer of6H—SiC, wherein said SiC substrate is a 4H—SiC substrate, both of saidp-type SiC film (2) and said n-type SiC film (3) are made of 6H—SiC, andsaid p-type SiC film (2) consisting of 6H—SiC is formed on said 4H—SiCsubstrate with said buffer layer of 6H—SiC therebetween.